Hot-Debug for Intel XScale Core Debug

Overview

The purpose of this white paper is to explain the benefits of and the implementation requirements for Hot-Debug for Intel XScale micro architecture I/O processors. Traditionally, when a debugger is used through a Joint Test Action Group (JTAG) connection, the processor is reset at the beginning of the debug session. For standalone applications, this is acceptable, but I/O processors are mostly used for Central Processing Unit (CPU) off load and add-in cards where there is a host system which configures all of the devices on the bus. The start of a debug session on an add-in card or a host bus adaptor causes a reset and consequently the bus configuration of the add-in card is lost.