Motivating Commodity Multi-Core Processor Design for System-Level Error Protection

Overview

This paper analyzes the reliability and availability features in several commodity Chip MultiProcessors (CMPs) and finds that they have numerous single points of failure. Failures in some system components, e.g., interconnect cache controller and memory controller logic, leave CMPs susceptible to error even if the computation is Dual Modular Redundant (DMR) or Triple Modular Redundant (TMR). Furthermore, even though some replicated resources are present in CMPs, they can not be used effectively for providing system-level protection because of the lack of fault isolation in shared components. This paper describes a CMP design that can provide system-level error protection. The proposed design provides mode configuration features in hardware to tolerate errors in any component.