Improving the Performance of Embedded Superscalar Microprocessors by Adding Partial Pipelines

Overview

This paper introduces adding a "Partial" pipeline to a base embedded superscalar microprocessor implementation to achieve cost effective performance improvements. This method is exemplified by adding a "Partial" Integer Pipeline (IP) to the TriCore TM 2.0 MCU/DSP core. The "Partial" IP pipeline, designed based on TriCore 2.0 simulation results of the EEMBC benchmark suite, executes a subset of TriCore 2.0 IP instructions. They used the basic block sampling and simulation technique to simulate enhanced TriCore 2.0 models, and obtained results indicating that adding the partial IP pipeline can achieve similar performance improvements to duplicating the full IP pipeline. Their approach can be applied to the early design stages of microprocessor development in order to explore design spaces.