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 TitleDate AddedCompany
whitepaper Genesys Enterprise Routing Solution V7.5 on IBM System p 570: Performance Report V1.02007-12-01 IBM
  An IBM System p 570 with an IBM POWER6 processor server running IBM AIX 5L Version 5.3.6 and IBM DB2 Universal Database Version 8.2.7 set an outstanding record on the Genesys Inbound Voice Solution v7.5 for the Inbound Call Center industry in September 2007. A 16-way IBM System p6 570 4.7 GHz IBM,9117-MMA server, configured as four Logical PARtitions (LPARs) using a total of 16 CPUs, demonstrated the scaling capabilities across three diverse configurations to meet the demands of an enterprise-level of Genesys' Inbound Voice solution and Reporting implementation. Just one LPAR has the capability of handling a Call Center with call activity of up to 80 calls per sec.

Tags: UNIX, 		  
whitepaper Parallel Processing Using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor2007-12-01 Waseda University
  Need for efficient processing of multimedia applications on PCs, mobile phones, games and so on have been increasing. Especially, low cost, low power consumption and high performance processors for multi-media applications have been expected. To satisfy the demands, chip multiprocessor architectures which allow giving scalability using multigrain parallelism are attracting much attention. However, to get performance of chip multiprocessor architectures, data locality optimization for target applications is also required. This paper describes a parallel processing scheme for MPEG2 encoding using data localization technique which improves execution efficiency by using global data locality optimization among different loops with coarse grain task parallel processing, and evaluates the performance of the proposal scheme on OSCAR chip multiprocessor architecture.

Tags: Parallel Processing		   
whitepaper Cache Optimization for Coarse Grain Task Parallel Processing Using Inter-Array Padding2007-12-01 Waseda University
  The wide use of multiprocessor system has been making automatic parallelizing compilers more important. To improve the performance of multiprocessor system more by compiler, multigrain parallelization is important. In multigrain parallelization, coarse grain task parallelism among loops and subroutines and near fine grain parallelism among statements is used in addition to the traditional loop parallelism. In addition, locality optimization to use cache effectively is also important for the performance improvement. This paper describes inter-array padding to minimize cache conflict misses among macro-tasks with data localization scheme which decomposes loops sharing the same arrays to fit cache size and executes the decomposed loops consecutively on the same processor.

Tags: Parallel Processing		   
whitepaper Intel Centrino With VPro Technology and Intel Core2 Processor With VPro Technology2007-12-01 Intel
  Intel Centrino with vPro technology-based notebooks and Intel Core2 processor with vPro technology-based desktop PCs1 deliver built-in security and remote management capabilities to meet critical business challenges. IT administrators can now quickly identify and contain more security threats, take more accurate asset and hardware/software inventories remotely, resolve more software and OS problems faster without leaving the service center, and accurately diagnose hardware problems down-the-wire. IT organizations can now spend less time on routine tasks, and can focus resources where they are most needed for better security and manageability of both notebook and desktop PCs.   
whitepaper Select Text and Graphics2007-12-01 Microsoft Tips
  One can select text and graphics by using the mouse or the keyboard, including items that aren't next to each other. For example, one can select a paragraph on page one and a sentence on page three. Microsoft Word provides additional methods for selecting items in a table, drawing objects, or text in outline view (outline view: A view that shows the headings of a document indented to represent their level in the document's structure. One can also use outline view to work with master documents.).

Tags: Word Processing		   
whitepaper Accelerating EDA Application Performance with 45nm Quad-Core Processors2007-11-20 Intel
  Intel IT and Synopsys conducted a joint performance assessment of 64-bit Intel multi-core platforms running Synopsys Proteus* application for optical proximity correction (OPC).

Tags: Embedded Microprocessors, Data Mining - Analysis, Database Management, Data Recovery - Security		   
whitepaper Performance Characterization of HP ProLiant DL360 G5 With Quad-Core Intel Xeon Processors (3.16 GHz/2x6 MB) in a 64-Bit HP Server Based Computing Environment2007-11-01 Hewlett-Packard (HP)
  This paper describes a performance characterization performed utilizing the HP 64-bit test harness, which incorporates a Microsoft Office 2003 workload. Test results cannot be compared directly with the results of tests performed using the 32-bit Office XP- or Office 2003-based harnesses. Combining concentrated 1U computing power, HP Integrated Lights-Out 2 (iLO 2) management, and essential fault tolerance, the HP ProLiant DL360 G5 server is a great choice for any business where space is at a premium.

Tags: High Performance Computing		   
whitepaper Introducing the 45nm Next-Generation Intel Core Microarchitecture2007-11-01 Intel
  In the second half of 2007, Intel started producing of the next-generation Intel Core2 processor family codenamed "Penryn." The Penryn processor family is based on industry-leading 45-nanometer (nm) High-k metal gate silicon technology and latest microarchitecture enhancements. This next evolution in Intel Core microarchitecture builds on the tremendous success of revolutionary microarchitecture and marks the next step in Intel's rapid cadence for delivering a new process technology with enhanced microarchitecture or an entirely new microarchitecture every year.   
whitepaper IBM POWER6 Microprocessor Physical Design and Design Methodology2007-11-01 IBM
  The IBM POWER6e microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, Random Logic Macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

Tags: Methodology		   
whitepaper System Power Management Support in the IBM POWER6 Microprocessor2007-11-01 IBM
  The IBM POWER6 microprocessor chip supports advanced, dynamic power management solutions for managing not just the chip but the entire server. The design facilitates a programmable power management solution for greater flexibility and integration into system- and data-center-wide management solutions. The design of the POWER6 microprocessor provides real-time access to detailed and accurate information on power, temperature, and performance. Together, the sensing, actuation, and management support available in the POWER6 processor, known as the EnergyScalee architecture, enables higher performance, greater energy efficiency, and new power management capabilities such as power and thermal capping and power savings with explicit performance control. This paper provides an overview of the innovative design of the POWER6 processor that enables these advanced, dynamic system power management solutions.