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Title Date Added Company

ACT: A Cluster Co-Processor for 3G Baseband Wireless 0000-00-00 Institute of Electrical and Electronics Engineers

Architectures for wireless systems have traditionally been designed to meet real-time requirements, t on a limited die area, and operate within a low power budget. These conditions are usually met by implementing compute-intensive operations in an Application Specific Integrated Circuit (ASIC). ASIC design is both expensive and time consuming. ASICs also suffer in that even minor evolutionary changes in the application invoke another ASIC design cycle. In the rapidly evolving wireless communication space these defects are severe. Flexibility can be achieved by reconfigurable architectures, and the ability to use special purpose configurations enhances both performance and energy efficiency. Often reconfigurable systems are based on FPGA devices which compromise both logic speed and power in order to achieve reconfigurability.

Tags: Mobile - Wireless Communications

Utilizing Intel Virtualization Technology on an Intel 5000 Chipset Series-Based Platform 2007-04-01 Intel

System architects in the Server and Workstation Multiprocessing environments have been actively using Virtualization Technology to realize cost savings through hardware consolidation, fast fail-over mechanisms (without extra hardware), and other beneficial use models. Now this technology has increased interest in the embedded and communication markets. This paper focuses on one common use case for virtualization in the embedded space, demonstrating a proof-of-concept for a solution where the processing resources of many computer terminals have been consolidated to a single hardware platform via a VMM providing many virtualized machines.

Tags: Virtualization

New Balance Uses HP Workstations to Design Footwear 2006-12-13 01:00:24 Hewlett-Packard

Footwear designers at New Balance required powerful, reliable computing hardware and software to help render three-dimensional CAD designs. The need for high-performance software and computer hardware is paramount for the designers in the race to get new footwear and apparel to market. Trends come and go at lightning speed. New Balance needs technology that helps accelerate product development while maintaining customers' performance, fit and design expectations. Shoe manufacturer purchased HP xw4300 Workstations to run SolidWorks CAD applications.

Intel Architecture and Silicon Cadence: The Catalyst for Industry Innovation 2006-12-27 01:00:55 Intel

Intel has a long history of setting the pace of industry innovation with the relentless pursuit of Moore's Law. This pace of innovation has served the ever increasing needs of users by providing the ability to increase processor performance, and deliver new features and capabilities, through innovation in processor architecture. As one looks at the continuation of this evolution, the industry needs an increased and more predictable pace of innovation to deliver platforms that can provide faster, more connected, trusted, personalized and natural computing experiences. Intel has embarked on a coordinated and accelerated pace of architecture innovation based on its industry-leading silicon expertise, and its architecture design capabilities that will provide the growth driver for the next decade and beyond.

Achieving High-Resolution Video Using Scalable Capture, Processing, and Display 2006-02-28 Hewlett-Packard (HP)

New video applications are becoming possible with the advent of several enabling technologies: multicamera capture, increased PC bus bandwidth, multicore processors, and advanced graphics cards. This paper presents a commercially-available multicamera system and a software architecture that, coupled with industry trends, create a situation in which video capture, processing, and display are all increasingly scalable in the number of video streams. Leveraging this end-to-end scalability, the authors introduce a novel method of generating high-resolution, panoramic video. While traditional point-based mosaicking requires significant image overlap, authors gain significant advantage by calibrating using shared observations of lines to constrain the placement of images.

Heterogeneous Chip Multiprocessors 2007-01-07 01:00:31 Institute of Electrical and Electronics Engineers

Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a much wider spectrum of system loads - from low to high thread parallelism - with high efficiency.

The Evolution of Build-Up Package Technology and Its Design Challenges 2006-04-04 02:54:05 IBM

This paper reviews Sequential Build-Up (SBU) laminate substrate development from its beginning in 1988. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for Application-Specific Integrated Circuit (ASIC) and microprocessor packaging applications.

Configuring DDR2 Memory on Dell Platforms Based on the Intel E7520 and E7525 Chip Sets 2005-09-15 03:00:04 Dell

In the summer of 2004, Dell introduced new dual-processor Power- Edge servers and Dell Precision workstations equipped with Intel Xeon processors with Extended Memory 64 Technology (EM64T). The workstations are based on the Intel E7525 chip set, formerly code-named "Tumwater," and most of the servers are based on the Intel E7520 chip set, formerly code-named "Lindenhurst." The E7520 and E7525 chip sets have flexible DDR2 memory subsystem implementation options. Dell worked closely with Intel to design server and workstation platforms that provide flexible DDR2 memory configuration options that meet a variety of customer requirements. This white paper provides guidance on how to configure Dell PowerEdge and Dell Precision systems based on the E7520 and E7525 chip sets.

The Role of Specialized Hardware in Network Security Gateways 2006-01-04 01:01:52 Check Point Software Technologies

This paper explores the potentials and pitfalls of using network security appliances running specialized Integrated Circuits (ICs). It offers a vision that includes a role for such ICs in offloading and accelerating specific and static network and security-related functions, but always within a larger context of a robust open-server architecture that allows critical security features to be quickly added and modified in software without sacrificing performance. Only this kind of architecture can adapt to the fast-changing nature of network security while fulfilling the ever-increasing performance requirements of customers. This paper also discusses the value of network security hardware that is based on open standards and APIs and of software-based solutions that can run on such platforms.

Decoding Convolutional and Turbo Codes in 3G Wireless 2005-06-10 03:00:02

Decoding of forward error correcting (FEC) codes is the most computationally intensive part of symbol-rate processing in a basestation receiver and could consume up to 90% of computing resources. This is true for both second generation (2G) and third generation (3G) systems. This paper compares three different implementation options for decoding in 3G wireless - software approach using DSPs, hardware approach using ASICs, and a combined software-hardware approach using on-chip accelerators.

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Title	Date Added	Company
ACT: A Cluster Co-Processor for 3G Baseband Wireless	0000-00-00	Institute of Electrical and Electronics Engineers
Architectures for wireless systems have traditionally been designed to meet real-time requirements, t on a limited die area, and operate within a low power budget. These conditions are usually met by implementing compute-intensive operations in an Application Specific Integrated Circuit (ASIC). ASIC design is both expensive and time consuming. ASICs also suffer in that even minor evolutionary changes in the application invoke another ASIC design cycle. In the rapidly evolving wireless communication space these defects are severe. Flexibility can be achieved by reconfigurable architectures, and the ability to use special purpose configurations enhances both performance and energy efficiency. Often reconfigurable systems are based on FPGA devices which compromise both logic speed and power in order to achieve reconfigurability. Tags: Mobile - Wireless Communications
Utilizing Intel Virtualization Technology on an Intel 5000 Chipset Series-Based Platform	2007-04-01	Intel
System architects in the Server and Workstation Multiprocessing environments have been actively using Virtualization Technology to realize cost savings through hardware consolidation, fast fail-over mechanisms (without extra hardware), and other beneficial use models. Now this technology has increased interest in the embedded and communication markets. This paper focuses on one common use case for virtualization in the embedded space, demonstrating a proof-of-concept for a solution where the processing resources of many computer terminals have been consolidated to a single hardware platform via a VMM providing many virtualized machines. Tags: Virtualization
New Balance Uses HP Workstations to Design Footwear	2006-12-13 01:00:24	Hewlett-Packard
Footwear designers at New Balance required powerful, reliable computing hardware and software to help render three-dimensional CAD designs. The need for high-performance software and computer hardware is paramount for the designers in the race to get new footwear and apparel to market. Trends come and go at lightning speed. New Balance needs technology that helps accelerate product development while maintaining customers' performance, fit and design expectations. Shoe manufacturer purchased HP xw4300 Workstations to run SolidWorks CAD applications.
Intel Architecture and Silicon Cadence: The Catalyst for Industry Innovation	2006-12-27 01:00:55	Intel
Intel has a long history of setting the pace of industry innovation with the relentless pursuit of Moore's Law. This pace of innovation has served the ever increasing needs of users by providing the ability to increase processor performance, and deliver new features and capabilities, through innovation in processor architecture. As one looks at the continuation of this evolution, the industry needs an increased and more predictable pace of innovation to deliver platforms that can provide faster, more connected, trusted, personalized and natural computing experiences. Intel has embarked on a coordinated and accelerated pace of architecture innovation based on its industry-leading silicon expertise, and its architecture design capabilities that will provide the growth driver for the next decade and beyond.
Achieving High-Resolution Video Using Scalable Capture, Processing, and Display	2006-02-28	Hewlett-Packard (HP)
New video applications are becoming possible with the advent of several enabling technologies: multicamera capture, increased PC bus bandwidth, multicore processors, and advanced graphics cards. This paper presents a commercially-available multicamera system and a software architecture that, coupled with industry trends, create a situation in which video capture, processing, and display are all increasingly scalable in the number of video streams. Leveraging this end-to-end scalability, the authors introduce a novel method of generating high-resolution, panoramic video. While traditional point-based mosaicking requires significant image overlap, authors gain significant advantage by calibrating using shared observations of lines to constrain the placement of images.
Heterogeneous Chip Multiprocessors	2007-01-07 01:00:31	Institute of Electrical and Electronics Engineers
Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a much wider spectrum of system loads - from low to high thread parallelism - with high efficiency.
The Evolution of Build-Up Package Technology and Its Design Challenges	2006-04-04 02:54:05	IBM
This paper reviews Sequential Build-Up (SBU) laminate substrate development from its beginning in 1988. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for Application-Specific Integrated Circuit (ASIC) and microprocessor packaging applications.
Configuring DDR2 Memory on Dell Platforms Based on the Intel E7520 and E7525 Chip Sets	2005-09-15 03:00:04	Dell
In the summer of 2004, Dell introduced new dual-processor Power- Edge servers and Dell Precision workstations equipped with Intel Xeon processors with Extended Memory 64 Technology (EM64T). The workstations are based on the Intel E7525 chip set, formerly code-named "Tumwater," and most of the servers are based on the Intel E7520 chip set, formerly code-named "Lindenhurst." The E7520 and E7525 chip sets have flexible DDR2 memory subsystem implementation options. Dell worked closely with Intel to design server and workstation platforms that provide flexible DDR2 memory configuration options that meet a variety of customer requirements. This white paper provides guidance on how to configure Dell PowerEdge and Dell Precision systems based on the E7520 and E7525 chip sets.
The Role of Specialized Hardware in Network Security Gateways	2006-01-04 01:01:52	Check Point Software Technologies
This paper explores the potentials and pitfalls of using network security appliances running specialized Integrated Circuits (ICs). It offers a vision that includes a role for such ICs in offloading and accelerating specific and static network and security-related functions, but always within a larger context of a robust open-server architecture that allows critical security features to be quickly added and modified in software without sacrificing performance. Only this kind of architecture can adapt to the fast-changing nature of network security while fulfilling the ever-increasing performance requirements of customers. This paper also discusses the value of network security hardware that is based on open standards and APIs and of software-based solutions that can run on such platforms.
Decoding Convolutional and Turbo Codes in 3G Wireless	2005-06-10 03:00:02
Decoding of forward error correcting (FEC) codes is the most computationally intensive part of symbol-rate processing in a basestation receiver and could consume up to 90% of computing resources. This is true for both second generation (2G) and third generation (3G) systems. This paper compares three different implementation options for decoding in 3G wireless - software approach using DSPs, hardware approach using ASICs, and a combined software-hardware approach using on-chip accelerators.