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Title Date Added Company

IP Eases Bluetooth Design 2005-11-15 01:00:02

Some of the main challenges in Bluetooth design occur at the embedded-system level, where developers have to determine the best level of chip integration for virtual components. The first question is whether to use off-the-shelf Bluetooth chips or to develop an application specific integrated circuit (ASIC) that integrates Bluetooth functions into an existing design. There is no easy answer, because electronic design involves balancing technology issues with business and marketing factors such as development and manufacturing costs, and time to market.

Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs 2006-03-23 04:55:53 IBM

With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. This paper proposes and demonstrates an algorithm for the automated placement and sizing of decaps in ASIC-like circuits.

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Title	Date Added	Company
IP Eases Bluetooth Design	2005-11-15 01:00:02
Some of the main challenges in Bluetooth design occur at the embedded-system level, where developers have to determine the best level of chip integration for virtual components. The first question is whether to use off-the-shelf Bluetooth chips or to develop an application specific integrated circuit (ASIC) that integrates Bluetooth functions into an existing design. There is no easy answer, because electronic design involves balancing technology issues with business and marketing factors such as development and manufacturing costs, and time to market.
Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs	2006-03-23 04:55:53	IBM
With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. This paper proposes and demonstrates an algorithm for the automated placement and sizing of decaps in ASIC-like circuits.