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 TitleDate AddedCompany
whitepaper IBM eServer pSeries Hardware Management Console Security0000-00-00 UniRecovery
  The pSeries Hardware Management Console (HMC) was introduced in 2001 at the same time as the POWER4 family of AIX 5L servers. It consists of a 32-bit Intel processor-based computer running a modified Linux operating system. The primary function of the HMC is to run a graphical user interface based on Java that provides management tools for controlling one or more POWER4 servers and associated Logical PARtitions (LPARs). This white paper describes what IBM has done to protect the HMC from unauthorized access or exploitation in a networked environment.

Tags: AIX, Linux Server OS		   
whitepaper Extending the World's Most Popular Processor Architecture: New Innovations That Improve the Performance and Energy Efficiency of Intel Architecture2006-09-01 Intel
  Intel has a long history of innovation in adding new capabilities to computer architecture and enabling the industry to deliver advanced applications with greater performance and capability. From the original Intel 8086 to the recent addition of Supplemental Streaming SIMD Extensions 3 (Supplemental SSE3) found in Intel Core 2 Duo processors, Intel has led the charge in expanding the capabilities of the world's most popular and broadly used computer architecture - Intel architecture. Continuing the history of innovation, this latest expansion of Intel architecture constitutes the most impactful instructions since SSE2 and represents the next major leap in Intel's fast-paced trajectory to deliver products with superior performance, capability, and energy-efficiency for years to come.

Tags: Application Development		   
whitepaper Intel Architecture and Silicon Cadence: The Catalyst for Industry Innovation2006-09-01 Intel
  Intel has a long history of setting the pace of industry innovation with the relentless pursuit of Moore's Law. This pace of innovation has served the ever increasing needs of users by providing the ability to increase processor performance, and deliver new features and capabilities, through innovation in processor architecture. As one looks at the continuation of this evolution, the industry needs an increased and more predictable pace of innovation to deliver platforms that can provide faster, more connected, trusted, personalized and natural computing experiences. Intel has embarked on a coordinated and accelerated pace of architecture innovation based on its industry-leading silicon expertise, and its architecture design capabilities that will provide the growth driver for the next decade and beyond.

Tags: ASICs - Chip Sets		   
whitepaper Harness the Power of Virtualization for Server Consolidation: Xen-Based Virtualization With SUSE Linux Enterprise on AMD Processors With AMD Virtualization2006-09-01 Novell
  Virtualization lets one to reduce the total number of servers by giving a person the ability to migrate multiple environments on different physical machines to individual virtual machines hosted on a single server. These virtual machines each run their own independent and self-contained operating systems and server applications. By consolidating multiple server environments onto a single server, one can harness more of the data center's unused computing power and get up to eight times more work from the same amount of resources. Virtualization also provides the added benefit of dynamic provisioning - moving applications and systems in one virtual machine from one server to another as needed.

Tags: Server Consolidation, Virtualization		   
whitepaper Adaptive Sensing and Image Processing With a General-Purpose Pixel-Parallel Sensor/Processor Array Integrated Circuit2006-09-01 Institute of Electrical and Electronics Engineers
  In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMP-3 vision chip, comprising 128 × 128 array, fabricated in a 0.35µm CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed.

Tags: Parallel Processing		   
whitepaper Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization2006-08-10 Intel
  The first generation of Intel Virtualization Technology (VT) for IA-32 and Itanium processors provides hardware support that simplifies processor virtualization, enabling reductions in Virtual Machine Monitor (VMM) software size and complexity. Resulting VMMs can support a wider range of legacy and future Operating Systems (OSs) on the same physical platform while maintaining high performance. In this paper, the authors provide details of the virtualization challenges posed by IA-32 and Itanium processors; present an overview and furnish details of VT-x (Intel Virtualization Technology for the IA-32 architecture) and VT-i (Intel Virtualization Technology for the Itanium architecture); show how VT-x and VT-i address virtualization challenges; and finally provide examples of usage of the VT-x and VT-i architecture.

Tags: Virtualization		   
whitepaper Performance of the AMD Opteron LS21 for IBM BladeCenter2006-08-01 IBM
  This paper examines the performance of the AMD Opteron LS21 for IBM BladeCenter, or LS21. The analysis includes memory bandwidth and latency using Stream and a proprietary benchmark, floating-point vector performance using High Performance Linpack (HPL) and performance of the SPEC CPU2000 speed and rate benchmarks. The real value proposition of the LS21 is its small form factor, ease of management and low-power consumption, at which the LS21 excels. So the question that the authors endeavored to answer is "Was performance sacrificed in the designing of this blade?" The findings presented in this paper demonstrate that, even with a processor speed limit of 2.6 GHz instead of 2.8 GHz, performance was in no way sacrificed.

Tags: Blades		   
whitepaper Floating Point Calculations and the ANSI C, C++, and Fortran Standard2006-08-01 Intel
  High application performance is an important goal of the Intel compilers, even at default optimization levels. A number of optimizations involve transformations including: evaluation of constant expressions at compile time, hoisting invariant expressions out of loops, and changes in the order of evaluation of expressions that are not consistent with a strict interpretation of the ANSI or ISO standards for C, C++, and Fortran. These can result in differences in rounding and small variations in floating point results, which may be more or less accurate than the ANSI-conformant result. The Intel compilers provide command-line options that request the compiler not to perform optimizations that may be inconsistent with strict ANSI standards.

Tags: Programming Languages, Application Development		   
whitepaper Programming XPP-III Processors2006-07-13 PACT XPP Technologies
  This white paper describes the programming methods and tools for XPP-III processors. First, the profiling and partitioning of a given application is discussed. Next, different methods of programming a XPP-III core are presented, separately for the sequential Function-PAEs (FNC-PAEs) and the XPP dataflow array (ALU-PAEs and RAM-PAEs). Finally, PACT's PSDS tools are described.

Tags: Programming Languages		   
whitepaper Open MPI: A High-Performance, Heterogeneous MPI2006-07-11 Institute of Electrical and Electronics Engineers
  The growth in the number of generally available, distributed, heterogeneous computing systems places increasing importance on the development of user-friendly tools that enable application developers to efficiently use these resources. Open MPI provides support for several aspects of heterogeneity within a single, open-source MPI implementation. Through careful abstractions, heterogeneous support maintains efficient use of uniform computational platforms. This paper describes Open MPI's architecture for heterogeneous network and processor support. A key design features of this implementation is the transparency to the application developer while maintaining very high levels of performance. This is demonstrated with the results of several numerical experiments.

Tags: High Performance Computing