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 TitleDate AddedCompany
whitepaper Dynamic Power Management for UML Modeled Applications on Multiprocessor SoC2006-12-20 Tampere University of Technology
  The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile. Application processes are considered as elementary units of distributed execution, and their mapping on a multiprocessor SoC can be dynamically changed at run-time. The approach on the dynamic power management balances utilized processor resources against current workload at runtime by observing the processor and workload statistics, re-evaluating the amount of required resources (i.e. the number of active processors), and re-mapping the application processes to the minimum set of active processors.

Tags: UML		   
whitepaper Managing CPU-Intensive Work on Uniprocessor LPARs2006-12-18 IBM
  Uniprocessor systems may exist as either an LPAR on a single-engine physical processor or as a "Small LPAR" on a larger n-way physical processor. For this discussion, a "Small LPAR" is one that is guaranteed less than 50% of an engine based on its assigned weight when the processor runs at capacity. Often, a minimum of two logical CPs will be assigned to these small LPARs because clients are concerned about uniprocessor systems. However, running a small LPAR as a 2-way can result in "Short engines" and cause performance problems. "Short engines" occur on busy processors when the number of logical CPs exceeds the number guaranteed to an LPAR based on its weight.

Tags: Mainframes		   
whitepaper Web Services on Devices2006-12-13 Microsoft
  New opportunities for using network-connected devices continue to expand rapidly across consumer, enterprise, and vertical device markets. This expansion is due to device technology advancements including faster and smaller processors, increased computational power, shrinking memory costs, and greater network connectivity. IP network connectivity provides a platform for rich interoperability experiences between devices, PCs, and Internet services. However, to achieve "USB-like" device growth, networked devices must use technologies that reduce complexity and provide setup, security, control, and cross-network connectivity standards. Microsoft's strategy for meeting these challenges is to use Web services. To support Web services on devices, Microsoft has provided native support in Windows Vista for the Devices Profile for Web Services (DPWS) standard.

Tags: Web Services, Windows Vista		   
whitepaper An FPGA-Based Dynamic Load-Balancing Processor Architecture for Solving N-Body Problems2006-12-13 Utah State University
  Reconfigurable computing has emerged as a key technology in the field of high performance and embedded computing. This research focuses on the use of reconfigurable processors for solving computationally intensive scientific applications, with an added twist. An architecture is designing that can retarget its resources dynamically based on run-time and data-driven variation in task level parallelism, as typically seen in radar-based target tracking, high performance video compression, and N-body simulations. The approach advocates the derivation of such runtime-reconfigurable architectures through a set of compile time analyses, integrating resource derivation and allocation with a set of architectural features that permit rapid run-time adaptation of reconfigurable data paths.

Tags: Processors, High Performance Computing		   
whitepaper Fast Elliptic Curve Cryptographic Processor Architecture Based on Three Parallel GF(2k) Bit Level Pipelined Digit Serial Multipliers2006-12-13 King Fahd University of Petroleum & Minerals
  Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2k) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2k) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography.

Tags: Parallel Processing		   
whitepaper HP sx2000 Chipset2006-12-01 Hewlett-Packard (HP)
  The HP sx2000 is an enterprise systems chipset that is designed to provide scalability, reliability, manageability and performance to meet the most demanding server needs. The chipset used in the latest HP Integrity and HP 9000 high-end and midrange servers, supports the new dual-core Intel Itanium 2 and Itanium 2 9M processors, while providing a foundation for the upcoming Itanium 2 "Montvale" processor. In addition, with the support of the HP PA-8900 RISC processors on the sx2000 chipset, HP Itanium 2 processors and PA-8900 RISC processors can concurrently operate in an HP Integrity Superdome in separate hard partitions. This provides the flexibility and longevity to maximize Return-On-Investment (ROI).

Tags: ASICs - Chip Sets, RISC-Based Servers		   
whitepaper Linux on HP Integrity Servers2006-12-01 Hewlett-Packard (HP)
  If one feels the constant pressure to deliver high-business-value services faster and more economically than ever before. What one need is a simplified IT environment - one that's easier and more cost-effective to manage and grow - but without giving up high performance and flexibility. To address this need, many organizations are increasingly turning to Linux as an open, economical operating system for enterprise-class computing. HP Integrity servers with Intel Itanium 2 processors can help to break free of proprietary architectures, consolidate the data centers, and simplify IT so one can put more of the valuable IT talent into innovation.

Tags: Application Servers, Linux - Open Source		   
whitepaper IBM and Novell: The SLES 10 Success Story2006-12-01 IBM
  Novell's SUSE Linux Enterprise Server (SLES) 10 delivers new functionality, improved scalability and increased performance. To enhance IBM solutions on System x, System p, System z, and BladeCenter servers, SLES 10 includes over 180 features requested by IBM. SLES 10 features support new IBM hardware (devices and processors), cross platform functionality, and interoperability of IBM middleware and hardware. IBM implemented customer requirements, gained community acceptance and performed extensive testing of SLES 10 on IBM platforms. IBM's collaboration with Novell has continued to advance the SLES enterprise solution, with fast time to production, new technology and superior quality.

Tags: Blades, Linux Server OS		   
whitepaper SUSE Linux Enterprise Desktop and AMD64 Processors2006-12-01 Novell
  One needs a cost-effective, easy-to-use, secure desktop - and one also needs choice. That's where Novell can help. The SUSE Linux Enterprise Desktop, combined with AMD64 solutions and multi-core technology, is the first enterprise Linux desktop to meet these needs. AMD and Novell have a proven track record of innovation that meets critical customer needs. SUSE Linux Enterprise engineers have been at the forefront of Linux development for more than 12 years, and the SUSE Linux Enterprise operating system has supported both 32- and 64-bit computing platforms from the very beginning. This made Novell a natural partner for AMD.

Tags: Linux - Open Source, Linux Server OS		   
whitepaper A Performance-Aware Speculation Control Technique Using Wrong Path Usefulness Prediction2006-12-01 Microsoft
  This paper proposes implementable Wrong-Path Usefulness Predictors (WPUPs) that can accurately predict whether or not wrong-path execution will be beneficial for performance. The WPUP is used in combination with a novel low-cost fetch gating scheme that does not require large specialized prediction structures to estimate if the processor is on the wrong path. If the WPUP predicts that wrong-path execution will be beneficial for performance, the fetch engine is not gated. The results show that this mechanism reduces the performance loss incurred by fetch gating mechanisms that assume wrong-path execution is useless, thereby both improving performance and reducing energy consumption.   


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