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Title Date Added Company

Genesys Enterprise Routing Solution V7.5 on IBM System p 570: Performance Report V1.0 2007-12-01 IBM

An IBM System p 570 with an IBM POWER6 processor server running IBM AIX 5L Version 5.3.6 and IBM DB2 Universal Database Version 8.2.7 set an outstanding record on the Genesys Inbound Voice Solution v7.5 for the Inbound Call Center industry in September 2007. A 16-way IBM System p6 570 4.7 GHz IBM,9117-MMA server, configured as four Logical PARtitions (LPARs) using a total of 16 CPUs, demonstrated the scaling capabilities across three diverse configurations to meet the demands of an enterprise-level of Genesys' Inbound Voice solution and Reporting implementation. Just one LPAR has the capability of handling a Call Center with call activity of up to 80 calls per sec.

Tags: UNIX,

Performance Characterization of HP ProLiant DL360 G5 With Quad-Core Intel Xeon Processors (3.16 GHz/2x6 MB) in a 64-Bit HP Server Based Computing Environment 2007-11-01 Hewlett-Packard (HP)

This paper describes a performance characterization performed utilizing the HP 64-bit test harness, which incorporates a Microsoft Office 2003 workload. Test results cannot be compared directly with the results of tests performed using the 32-bit Office XP- or Office 2003-based harnesses. Combining concentrated 1U computing power, HP Integrated Lights-Out 2 (iLO 2) management, and essential fault tolerance, the HP ProLiant DL360 G5 server is a great choice for any business where space is at a premium.

Tags: High Performance Computing

Huawei ATCA Blade Server Powered by AMD Opteron Processors 2007-10-22 Advanced Micro Devices (AMD)

When AMD first introduced the AMD Opteron processor with Direct Connect Architecture in 2003, the target market was for servers in the datacenter. Back then, AMD had a new vision for how system memory and I/O interface to the processor core as well as the ability to create the world's first native dual-core and quad-core x86 processors. These technological advances by AMD have also brought out a new metric called "Performance per watt" which is frequently used as a way to measure overall processor effectiveness. Besides the traditional server market, AMD Opteron processors are also being used for high-end embedded applications. The AMD64 superscalar processor family features Direct Connect Architecture with an integrated memory controller, a scalable high-speed HyperTransport technology I/O interface and industry-leading x86 processor performance.

Tags: Blades

Intel Centrino Pro and Intel vProProcessor Technology 2007-09-05 Intel

Remotely manage both wired and wireless PCs from the same IT console to increase security and simplify system management A new generation of notebook and desktop PCs provides proactive security, enhanced maintenance, and improved remote management. Notebook PCs with Intel Centrino Pro processor technology and desktop PCs with Intel vPro processor technology deliver down-the-wire security and manageability capabilities even if hardware (such as a hard drive) has failed, the operating system is unresponsive, software agents are disabled, a desktop PC's power is off, or a notebook's management agents have been disabled. Desktop PCs also include support for virtual appliances that allows IT managers to isolate and protect critical security and management applications in a tamper-resistant environment. In addition, the new generation of notebook and desktop systems delivers significantly improved performance for compute-intensive tasks all in a power-efficient package that is Microsoft Windows Vista* ready.

MCA Error Recovery: HP-UX Feature for Recovering From Machine Check Aborts 2007-09-01 Hewlett-Packard (HP)

HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure. Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).

Tags: HP-UX

Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation 0000-00-00 IBM

The initial state of a design under verification has a major impact on the ability of stimuli generators to successfully generate the requested stimuli. For complexity reasons, most stimuli generators use sequential solutions without planning ahead. Therefore, in many cases they fail to produce a consistent stimulus due to an inadequate selection of the initial state. This paper proposes a new method, based on machine learning techniques, to improve generation success by learning the relationship between the initial state vector and generation success. The paper applies the proposed method in two different settings, with the objective of improving generation success and coverage in processor and system level generation. In both settings, the proposed method significantly reduced generation failures and enabled faster coverage.

Tags: Learning Management Systems,

Datacenter-on-Chip Architectures: Tera-Scale Opportunities and Challenges 2007-08-22 Intel

The world has entered in an era of Chip MultiProcessor (CMP) platforms, where performance is delivered with the integration of more and more cores on a die. Tera-scale CMP architectures, consisting of several tens of physical cores and hundreds of hardware threads, are highly suitable for throughput computing especially in the server market place. This paper starts by highlighting tera-scale potential in datacenter environments. It shows how a multi-tier datacenter workload that required tens (to hundreds) of platforms in the past can potentially map on to one (or a few) single-socket tera-scale CMP platforms running Virtual Machines (VMs) and thereby creating Datacenter-on-Chip (DoC) architectures.

Tags: Data Center

Scalable Performance for Server Consolidation in Virtualized Environments 2007-08-01 Intel

In Intel IT tests, a four-socket server based on the Quad-Core Intel Xeon processor 7300 series demonstrated scalable, predictable performance with up to 32 consolidated server workloads in Virtual Machines (VMs). As the paper added CPU-intensive workloads to the server, average workload runtimes remained approximately constant until one reached 16 VMs. Runtimes then increased at a predictable, linear rate as one continued to add workloads, up to a total of 32. With a dual-socket server based on the Quad-Core Intel Xeon processor 5300 series, runtimes began to increase at about eight VMs, and with a dual-socket server based on the Dual-Core Intel Xeon processor 5100 series, runtimes began to increase at about four VMs.

Tags: Server Consolidation, Virtualization

Improving Source Code Security and Quality Using Intel Compilers 2007-08-01 Intel

Compilers diagnostics capabilities have increased rapidly in recent years. Intel C++ and Fortran Compilers provide features that can enhance application security, improve source code quality and reliability. This paper is written for software developers and managers who want to learn the state of the art compiler diagnostic capabilities available in Intel C++ and Fortran Compilers. The Static Verifier, new in Intel Compilers version 10.0, detects incorrect or questionable C, C++, and Fortran source code usage including OpenMP, at compile time. The Static Verifier, together with stack and buffer overflow run time checks can detect certain common security vulnerabilities.

Tags: Programming Languages, Security Management

Intelligent Perceptual Information Parallel Processing System Controlled by Mathematical AIM Model 2007-07-27 University of Tsukuba

This paper studies an intelligent perceptual information processing system in which plural processing can run in parallel. The proposed mathematical Activation-Input-Modulation (AIM) model controls each execution frequency of plural processing independently based on degrees of stimuli detected by external sensors. When external stimuli are detected by some of external sensors, information processing tasks related to the sensors have a priority to be executed, and the stimuli are stored in a memory system. When no external stimulus is detected, the execution frequencies of almost external information processing decrease, and information stored in the memory system is organized by internal information processors.

Tags: Parallel Processing

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Title	Date Added	Company
Genesys Enterprise Routing Solution V7.5 on IBM System p 570: Performance Report V1.0	2007-12-01	IBM
An IBM System p 570 with an IBM POWER6 processor server running IBM AIX 5L Version 5.3.6 and IBM DB2 Universal Database Version 8.2.7 set an outstanding record on the Genesys Inbound Voice Solution v7.5 for the Inbound Call Center industry in September 2007. A 16-way IBM System p6 570 4.7 GHz IBM,9117-MMA server, configured as four Logical PARtitions (LPARs) using a total of 16 CPUs, demonstrated the scaling capabilities across three diverse configurations to meet the demands of an enterprise-level of Genesys' Inbound Voice solution and Reporting implementation. Just one LPAR has the capability of handling a Call Center with call activity of up to 80 calls per sec. Tags: UNIX,
Performance Characterization of HP ProLiant DL360 G5 With Quad-Core Intel Xeon Processors (3.16 GHz/2x6 MB) in a 64-Bit HP Server Based Computing Environment	2007-11-01	Hewlett-Packard (HP)
This paper describes a performance characterization performed utilizing the HP 64-bit test harness, which incorporates a Microsoft Office 2003 workload. Test results cannot be compared directly with the results of tests performed using the 32-bit Office XP- or Office 2003-based harnesses. Combining concentrated 1U computing power, HP Integrated Lights-Out 2 (iLO 2) management, and essential fault tolerance, the HP ProLiant DL360 G5 server is a great choice for any business where space is at a premium. Tags: High Performance Computing
Huawei ATCA Blade Server Powered by AMD Opteron Processors	2007-10-22	Advanced Micro Devices (AMD)
When AMD first introduced the AMD Opteron processor with Direct Connect Architecture in 2003, the target market was for servers in the datacenter. Back then, AMD had a new vision for how system memory and I/O interface to the processor core as well as the ability to create the world's first native dual-core and quad-core x86 processors. These technological advances by AMD have also brought out a new metric called "Performance per watt" which is frequently used as a way to measure overall processor effectiveness. Besides the traditional server market, AMD Opteron processors are also being used for high-end embedded applications. The AMD64 superscalar processor family features Direct Connect Architecture with an integrated memory controller, a scalable high-speed HyperTransport technology I/O interface and industry-leading x86 processor performance. Tags: Blades
Intel Centrino Pro and Intel vProProcessor Technology	2007-09-05	Intel
Remotely manage both wired and wireless PCs from the same IT console to increase security and simplify system management A new generation of notebook and desktop PCs provides proactive security, enhanced maintenance, and improved remote management. Notebook PCs with Intel Centrino Pro processor technology and desktop PCs with Intel vPro processor technology deliver down-the-wire security and manageability capabilities even if hardware (such as a hard drive) has failed, the operating system is unresponsive, software agents are disabled, a desktop PC's power is off, or a notebook's management agents have been disabled. Desktop PCs also include support for virtual appliances that allows IT managers to isolate and protect critical security and management applications in a tamper-resistant environment. In addition, the new generation of notebook and desktop systems delivers significantly improved performance for compute-intensive tasks all in a power-efficient package that is Microsoft Windows Vista* ready.
MCA Error Recovery: HP-UX Feature for Recovering From Machine Check Aborts	2007-09-01	Hewlett-Packard (HP)
HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure. Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs). Tags: HP-UX
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation	0000-00-00	IBM
The initial state of a design under verification has a major impact on the ability of stimuli generators to successfully generate the requested stimuli. For complexity reasons, most stimuli generators use sequential solutions without planning ahead. Therefore, in many cases they fail to produce a consistent stimulus due to an inadequate selection of the initial state. This paper proposes a new method, based on machine learning techniques, to improve generation success by learning the relationship between the initial state vector and generation success. The paper applies the proposed method in two different settings, with the objective of improving generation success and coverage in processor and system level generation. In both settings, the proposed method significantly reduced generation failures and enabled faster coverage. Tags: Learning Management Systems,
Datacenter-on-Chip Architectures: Tera-Scale Opportunities and Challenges	2007-08-22	Intel
The world has entered in an era of Chip MultiProcessor (CMP) platforms, where performance is delivered with the integration of more and more cores on a die. Tera-scale CMP architectures, consisting of several tens of physical cores and hundreds of hardware threads, are highly suitable for throughput computing especially in the server market place. This paper starts by highlighting tera-scale potential in datacenter environments. It shows how a multi-tier datacenter workload that required tens (to hundreds) of platforms in the past can potentially map on to one (or a few) single-socket tera-scale CMP platforms running Virtual Machines (VMs) and thereby creating Datacenter-on-Chip (DoC) architectures. Tags: Data Center
Scalable Performance for Server Consolidation in Virtualized Environments	2007-08-01	Intel
In Intel IT tests, a four-socket server based on the Quad-Core Intel Xeon processor 7300 series demonstrated scalable, predictable performance with up to 32 consolidated server workloads in Virtual Machines (VMs). As the paper added CPU-intensive workloads to the server, average workload runtimes remained approximately constant until one reached 16 VMs. Runtimes then increased at a predictable, linear rate as one continued to add workloads, up to a total of 32. With a dual-socket server based on the Quad-Core Intel Xeon processor 5300 series, runtimes began to increase at about eight VMs, and with a dual-socket server based on the Dual-Core Intel Xeon processor 5100 series, runtimes began to increase at about four VMs. Tags: Server Consolidation, Virtualization
Improving Source Code Security and Quality Using Intel Compilers	2007-08-01	Intel
Compilers diagnostics capabilities have increased rapidly in recent years. Intel C++ and Fortran Compilers provide features that can enhance application security, improve source code quality and reliability. This paper is written for software developers and managers who want to learn the state of the art compiler diagnostic capabilities available in Intel C++ and Fortran Compilers. The Static Verifier, new in Intel Compilers version 10.0, detects incorrect or questionable C, C++, and Fortran source code usage including OpenMP, at compile time. The Static Verifier, together with stack and buffer overflow run time checks can detect certain common security vulnerabilities. Tags: Programming Languages, Security Management
Intelligent Perceptual Information Parallel Processing System Controlled by Mathematical AIM Model	2007-07-27	University of Tsukuba
This paper studies an intelligent perceptual information processing system in which plural processing can run in parallel. The proposed mathematical Activation-Input-Modulation (AIM) model controls each execution frequency of plural processing independently based on degrees of stimuli detected by external sensors. When external stimuli are detected by some of external sensors, information processing tasks related to the sensors have a priority to be executed, and the stimuli are stored in a memory system. When no external stimulus is detected, the execution frequencies of almost external information processing decrease, and information stored in the memory system is organized by internal information processors. Tags: Parallel Processing