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 TitleDate AddedCompany
whitepaper Analyzing Performance Vulnerability Due to Resource Denial-of-Service Attack on Chip Multiprocessors2008-01-01 Georgia Institute of Technology
  Due to the ever-increasing design complexity and physical constraint in frequency scaling, chip multiprocessors are considered the de facto architecture baseline for future processor generation. Through resource sharing, applications running on a CMP can achieve better resource utilization and faster inter-core communication, leading to a higher overall throughput for the entire system. From a different perspective, however, such architectures are also more susceptible to Denial-of-Service (DoS) attacks on these shared resources, increasing the vulnerability in performance. Furthermore, as the number of cores increases, attacks similar to Distributed Denial-of-Service (DDoS) attacks on the Internet can be employed to throttle these on-chip resources with the presence of multiple malicious applications.

Tags: Network Security, Denial of Service		   
whitepaper Unix as an Application Program2008-01-01 Carnegie Mellon University
  Off late the author has had running at CMU a computing environment in which the functions of a traditional Unix system are cleanly divided into two parts: facilities which manage the hardware resources of a computer system (such as CPU, I/O and memory) and support for higher-level resource abstractions used in the building of application programs, e.g. files and sockets. This paper describes the implementation of Unix as a multithreaded application program running on the Mach kernel. The rationale, design, implementation history and performance of the system is presented.

Tags: UNIX		   
whitepaper MultiMATLAB: MATLAB on Multiple Processors2008-01-01 Cornell University
  MATLAB, a commercial product of The MathWorks, Inc., has become one of the principal languages of desktop scientific computing. A system is described that enables one to run MATLAB conveniently on multiple processors. Using short, MATLAB-style commands like Eval, Send, Recv, Bcast, Min, and Sum, the user operating within one MATLAB session can start MATLAB processes on other machines and then pass commands and data between between these various processes in a fashion that maintains MATLAB's traditional user-friendliness. Multi-processor graphics is also supported. The system currently runs under MPICH on an IBM SP2 or a network of Unix workstations, and extensions are planned to networks of PCs.

Tags: Workstations		   
whitepaper High Performance File I/O for the Blue Gene/L Supercomputer2008-01-01 IBM
  Parallel I/O plays a crucial role for most data-intensive applications running on massively parallel systems like Blue Gene/L that provides the promise of delivering enormous computational capability. This paper demonstrates the impact of the high performance I/O solution for Blue Gene/L with a comprehensive evaluation that consists of a number of widely used parallel I/O benchmarks and I/O intensive applications. The design and implementation is not only able to deliver at least one order of magnitude speed up in terms of I/O bandwidth for a real-scale application HOMME, but also supports high-level parallel I/O data interfaces such as parallel HDF5 and parallel NetCDF scaling up to a large number of processors.

Tags: Supercomputers, High Performance Computing		   
whitepaper Achieving Computational I/O Efficiency in a High Performance Cluster Using Multicore Processors2008-01-01 Tennessee Technological University
  Cluster computing has become one of the most popular platforms for high-performance computing today. The recent popularity of multicore processors provides a flexible way to increase the computational capability of clusters. Although the system performance may improve with multicore processors in a cluster, I/O requests initiated by multiple cores may saturate the I/O bus, and furthermore increase the latency by issuing multiple non-contiguous disk accesses. This paper proposes an asymmetric collective I/O for multicore processors to improve multiple non-contiguous accesses. In the configuration, one core in each multicore processor is designated as the coordinator, and others serve as computing cores. The coordinator is responsible for aggregating I/O operations from computing cores and submitting a contiguous request.

Tags: High Performance Computing		   
whitepaper High Performance Computing by Context Switching Reconfigurable Logic2008-01-01 University of Oslo
  Reconfigurable computing has grown to become an important and large field of research. It is based on using Field Programmable Gate Arrays (FPGAs). In this paper, this technology is introduced and it is shown how it can be applied for high speed computing. There is a large range of real-world applications for such systems, including image recognition and signal processing.

Tags: High Performance Computing		   
whitepaper RISC Processor Based Speech Codec Implementation for Emerging Mobile Multimedia Messaging Solutions2008-01-01 Aricent
  Mobile Multimedia Messaging (MMS) promises to provide a richer and versatile experience to the user along with new revenue streams for mobile service operators. MMS allows a full content range including images, audio, video and text in any combination. It delivers a location independent, total communication experience to the mobile customer. As proved by the success of Short Message Service (SMS) in generating revenue MMS applications would be the essential drivers of continuous growth in new services beyond voice. This paper describes the challenges and techniques of implementing speech codecs on RISC processors. The specific speech codec implemented was GSM-AMR and the processor used was ARM9TDMI.

Tags: RISC-Based Servers, Mobile - Wireless Communications		   
whitepaper Fast Secure Processor for Inhibiting Software Piracy and Tampering2008-01-01 University of California
  Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation is that other than the processor, any component is vulnerable to security attacks. Recently, an eXecution Only Memory (XOM) architecture has been proposed to support copy and tamper resistant software. This paper presents an innovative technique in which the cryptography computation is shifted off from the memory access critical path. They performed experiments to study the trade-off between storage size and performance penalty. The technique improves the execution speed of the XOM architecture by 34.7% at maximum.

Tags: Network Security		   
whitepaper Design Space Exploration of Network Processor Architectures2008-01-01 ETH Zurich
  This paper describes an approach to explore the design space for architectures of packet processing devices on the system level. The method is specific to the application domain of packet processors and is based on models for packet processing tasks, a specification of the workload generated by traffic streams, and a description of the feasible space of architectures including computation and communication resources, a measure to characterize the performance of network processors under different usage scenarios, a new method to estimate end-to-end packet delays and queuing memory, taking task scheduling policies and bus arbitration schemes into account, and a evolutionary algorithm for multi-objective design space exploration.

Tags: Application Development		   
whitepaper Live Migration With AMD-V Extended Migration Technology2007-12-17 Advanced Micro Devices (AMD)
  Virtual Machine migration is a capability being increasingly utilized in today's enterprise environments. With live migration, a Virtual Machine Monitor (VMM) moves a running Virtual Machine (VM) nearly instantaneously from one server to another for a seamless experience to the end user while maintaining guest uptime. However, if the processors running in the computers in the pre and post migration environment are not identical, live migration can result in unexpected behavior of the guest software. Since the introduction of its AMD64 processor technology in 2003, AMD has worked closely with virtualization software developers to define the functionality necessary to ensure that live migration is possible across a broad range of AMD64 processors.

Tags: Upgrades and Migration, Virtualization