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 TitleDate AddedCompany
whitepaper Tuning Symantec Brightmail AntiSpam on UltraSPARC T1 and T2 Processor-Powered Servers2007-12-07 Sun Microsystems
  Electronic mail is a business-critical function in virtually every enterprise, and it is also one that is under constant attack. Well-known viruses such as Melissa, and worms like SoBig have propagated through email and have disrupted user PCs and corporate networks worldwide. Fraudulent email messages find their ways into inboxes and tempt unsuspecting users into divulging personal information at phishing sites. As companies recognize that their intellectual property can easily leave their premises through email messages, filtering outbound and internal messages is becoming as important as protecting an organization from incoming traffic.

Tags: Network Security, Spam - E-mail Fraud - Phishing		   
whitepaper AMD Stream Computing: Software Stack2007-12-06 Advanced Micro Devices (AMD)
  Advanced Micro Devices, Inc. (AMD) - a leading global provider of innovative computing solutions - is working with other leading companies and academic institutions worldwide to deliver a complete, accelerated computing ecosystem with software and tools necessary to turn its high performance, low cost, supercomputing vision into reality. AMD's Stream Computing initiative is ushering processing technologies into the accelerated computing era through integration of CPU, GPU and complete software stack. AMD Stream Computing is a first step in harnessing the tremendous processing power the GPU (Stream Processor) for high performance, data-parallel computing in a wide range of business, scientific and consumer applications.

Tags: High Performance Computing		   
whitepaper Parallel Processing Using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor2007-12-01 Waseda University
  Need for efficient processing of multimedia applications on PCs, mobile phones, games and so on have been increasing. Especially, low cost, low power consumption and high performance processors for multi-media applications have been expected. To satisfy the demands, chip multiprocessor architectures which allow giving scalability using multigrain parallelism are attracting much attention. However, to get performance of chip multiprocessor architectures, data locality optimization for target applications is also required. This paper describes a parallel processing scheme for MPEG2 encoding using data localization technique which improves execution efficiency by using global data locality optimization among different loops with coarse grain task parallel processing, and evaluates the performance of the proposal scheme on OSCAR chip multiprocessor architecture.

Tags: Parallel Processing		   
whitepaper Cache Optimization for Coarse Grain Task Parallel Processing Using Inter-Array Padding2007-12-01 Waseda University
  The wide use of multiprocessor system has been making automatic parallelizing compilers more important. To improve the performance of multiprocessor system more by compiler, multigrain parallelization is important. In multigrain parallelization, coarse grain task parallelism among loops and subroutines and near fine grain parallelism among statements is used in addition to the traditional loop parallelism. In addition, locality optimization to use cache effectively is also important for the performance improvement. This paper describes inter-array padding to minimize cache conflict misses among macro-tasks with data localization scheme which decomposes loops sharing the same arrays to fit cache size and executes the decomposed loops consecutively on the same processor.

Tags: Parallel Processing		   
whitepaper Genesys Enterprise Routing Solution V7.5 on IBM System p 570: Performance Report V1.02007-12-01 IBM
  An IBM System p 570 with an IBM POWER6 processor server running IBM AIX 5L Version 5.3.6 and IBM DB2 Universal Database Version 8.2.7 set an outstanding record on the Genesys Inbound Voice Solution v7.5 for the Inbound Call Center industry in September 2007. A 16-way IBM System p6 570 4.7 GHz IBM,9117-MMA server, configured as four Logical PARtitions (LPARs) using a total of 16 CPUs, demonstrated the scaling capabilities across three diverse configurations to meet the demands of an enterprise-level of Genesys' Inbound Voice solution and Reporting implementation. Just one LPAR has the capability of handling a Call Center with call activity of up to 80 calls per sec.

Tags: UNIX		   
whitepaper A Super Scalar Sort Algorithm for RISC Processors2007-11-07 IBM
  The compare and branch sequences required in a traditional sort algorithm can not efficiently exploit multiple execution units present in currently available high performance RISC processors. This is because of the long latency of the compare instructions and the sequential algorithm used in sorting. With the increased level of integration on a chip, this trend is expected to continue. The paper has developed new sort algorithms which eliminate almost all the compares, provide functional parallelism which can be exploited by multiple execution units, significantly reduce the number of passes through keys, and improve data locality. These new algorithms outperform traditional sort algorithms by a large factor.

Tags: RISC-Based Servers		   
whitepaper Performance Characterization of HP ProLiant DL360 G5 With Quad-Core Intel Xeon Processors (3.16 GHz/2x6 MB) in a 64-Bit HP Server Based Computing Environment2007-11-01 Hewlett-Packard (HP)
  This paper describes a performance characterization performed utilizing the HP 64-bit test harness, which incorporates a Microsoft Office 2003 workload. Test results cannot be compared directly with the results of tests performed using the 32-bit Office XP- or Office 2003-based harnesses. Combining concentrated 1U computing power, HP Integrated Lights-Out 2 (iLO 2) management, and essential fault tolerance, the HP ProLiant DL360 G5 server is a great choice for any business where space is at a premium.

Tags: High Performance Computing		   
whitepaper Huawei ATCA Blade Server Powered by AMD Opteron Processors2007-10-22 Advanced Micro Devices (AMD)
  When AMD first introduced the AMD Opteron processor with Direct Connect Architecture in 2003, the target market was for servers in the datacenter. Back then, AMD had a new vision for how system memory and I/O interface to the processor core as well as the ability to create the world's first native dual-core and quad-core x86 processors. These technological advances by AMD have also brought out a new metric called "Performance per watt" which is frequently used as a way to measure overall processor effectiveness. Besides the traditional server market, AMD Opteron processors are also being used for high-end embedded applications. The AMD64 superscalar processor family features Direct Connect Architecture with an integrated memory controller, a scalable high-speed HyperTransport technology I/O interface and industry-leading x86 processor performance.

Tags: Blades		   
whitepaper Accelerating High-Performance Computing With FPGAs2007-10-01 Altera
  The coprocessors from Xtreme Data and SRC represent the next step in HPC. The competitive advantages that application speed gives to users ensures that the demand for speed will continue to outpace what processors alone can achieve. Coprocessors based on Stratix III FPGAs provide the high-speed, low-latency interfaces that hardware acceleration requires, while the tool chains and other support that Altera's partners offer simplify the creation of customized acceleration that HPC users demand. These tools and products are commercially available today as proven, high-performance solutions, and Altera's continuing partnership efforts ensure that these parts, products, and tools will continue to keep pace with future HPC needs.

Tags: High Performance Computing		   
whitepaper Optimization of Frequent Itemset Mining on Multiple-Core Processor2007-09-28 Association for Computing Machinery
  Multi-core processors are proliferated across different domains in recent years. This paper studies the performance of frequent pattern mining on a modern multi-core machine. A detailed study shows that, even with the best implementation, current FP-tree based algorithms still under-utilize a multi-core system due to poor data locality and insufficient parallelism expression. The paper proposes two techniques, a cache-conscious FP-array (frequent pattern array) and a lock-free dataset tiling parallelization mechanism to address this problem. The FP-array efficiently improves the data locality performance, and makes use of the benefits from hardware and software prefetching.

Tags: Parallel Processing