Member Login

E-mail:    Password:  




 TitleDate AddedCompany
whitepaper Intel Centrino Pro and Intel vProProcessor Technology2007-09-05 Intel
  Remotely manage both wired and wireless PCs from the same IT console to increase security and simplify system management A new generation of notebook and desktop PCs provides proactive security, enhanced maintenance, and improved remote management. Notebook PCs with Intel Centrino Pro processor technology and desktop PCs with Intel vPro processor technology deliver down-the-wire security and manageability capabilities even if hardware (such as a hard drive) has failed, the operating system is unresponsive, software agents are disabled, a desktop PC's power is off, or a notebook's management agents have been disabled. Desktop PCs also include support for virtual appliances that allows IT managers to isolate and protect critical security and management applications in a tamper-resistant environment. In addition, the new generation of notebook and desktop systems delivers significantly improved performance for compute-intensive tasks all in a power-efficient package that is Microsoft Windows Vista* ready.   
whitepaper MCA Error Recovery: HP-UX Feature for Recovering From Machine Check Aborts2007-09-01 Hewlett-Packard (HP)
  HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure. Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).

Tags: HP-UX		   
whitepaper Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation0000-00-00 IBM
  The initial state of a design under verification has a major impact on the ability of stimuli generators to successfully generate the requested stimuli. For complexity reasons, most stimuli generators use sequential solutions without planning ahead. Therefore, in many cases they fail to produce a consistent stimulus due to an inadequate selection of the initial state. This paper proposes a new method, based on machine learning techniques, to improve generation success by learning the relationship between the initial state vector and generation success. The paper applies the proposed method in two different settings, with the objective of improving generation success and coverage in processor and system level generation. In both settings, the proposed method significantly reduced generation failures and enabled faster coverage.

Tags: Learning Management Systems		   
whitepaper Datacenter-on-Chip Architectures: Tera-Scale Opportunities and Challenges2007-08-22 Intel
  The world has entered in an era of Chip MultiProcessor (CMP) platforms, where performance is delivered with the integration of more and more cores on a die. Tera-scale CMP architectures, consisting of several tens of physical cores and hundreds of hardware threads, are highly suitable for throughput computing especially in the server market place. This paper starts by highlighting tera-scale potential in datacenter environments. It shows how a multi-tier datacenter workload that required tens (to hundreds) of platforms in the past can potentially map on to one (or a few) single-socket tera-scale CMP platforms running Virtual Machines (VMs) and thereby creating Datacenter-on-Chip (DoC) architectures.

Tags: Data Center		   
whitepaper Scalable Performance for Server Consolidation in Virtualized Environments2007-08-01 Intel
  In Intel IT tests, a four-socket server based on the Quad-Core Intel Xeon processor 7300 series demonstrated scalable, predictable performance with up to 32 consolidated server workloads in Virtual Machines (VMs). As the paper added CPU-intensive workloads to the server, average workload runtimes remained approximately constant until one reached 16 VMs. Runtimes then increased at a predictable, linear rate as one continued to add workloads, up to a total of 32. With a dual-socket server based on the Quad-Core Intel Xeon processor 5300 series, runtimes began to increase at about eight VMs, and with a dual-socket server based on the Dual-Core Intel Xeon processor 5100 series, runtimes began to increase at about four VMs.

Tags: Server Consolidation, Virtualization		   
whitepaper Improving Source Code Security and Quality Using Intel Compilers2007-08-01 Intel
  Compilers diagnostics capabilities have increased rapidly in recent years. Intel C++ and Fortran Compilers provide features that can enhance application security, improve source code quality and reliability. This paper is written for software developers and managers who want to learn the state of the art compiler diagnostic capabilities available in Intel C++ and Fortran Compilers. The Static Verifier, new in Intel Compilers version 10.0, detects incorrect or questionable C, C++, and Fortran source code usage including OpenMP, at compile time. The Static Verifier, together with stack and buffer overflow run time checks can detect certain common security vulnerabilities.

Tags: Programming Languages, Security Management		   
whitepaper Intelligent Perceptual Information Parallel Processing System Controlled by Mathematical AIM Model2007-07-27 University of Tsukuba
  This paper studies an intelligent perceptual information processing system in which plural processing can run in parallel. The proposed mathematical Activation-Input-Modulation (AIM) model controls each execution frequency of plural processing independently based on degrees of stimuli detected by external sensors. When external stimuli are detected by some of external sensors, information processing tasks related to the sensors have a priority to be executed, and the stimuli are stored in a memory system. When no external stimulus is detected, the execution frequencies of almost external information processing decrease, and information stored in the memory system is organized by internal information processors.

Tags: Parallel Processing		   
whitepaper Operating System Scheduling on Heterogeneous Core Systems2007-07-23 Sun Microsystems
  This paper makes a case that a thread scheduler for heterogeneous multicore systems should target three objectives: optimal performance, core assignment balance and response time fairness. Performance optimization via optimal thread-to-core assignment has been explored in the past; this paper demonstrates the need for balanced core assignment. The paper shows that unbalanced core assignment results in completion time jitter and inconsistent priority enforcement; it then presents a simple fix to the Linux scheduler that eliminates these problems. The second part of the paper addresses the problem of building the HMC scheduler that balances all three objectives. This is a difficult optimization problem.

Tags: Software Engineering		   
whitepaper Implementation of Parallel Algorithm "Conveyer Processing" for Images Processing by Filter 'Mean'2007-07-04 Technical University of Sofia
  This paper implements a parallel algorithm for recursive image processing by filter 'Mean'. For implementation of parallel program is used MPI (Message Passing Interface) library. It is shown execution of a program with one and more processors. The program works with 24-bit BMP images. It is made a comparison between sequential and parallel "Conveyer processing" algorithms.

Tags: Parallel Processing, Software Engineering		   
whitepaper Compliance Risk Management2007-07-03 Advanced Micro Devices (AMD)
  The financial services industry is experiencing tremendous growth, diversification and innovation. Derivatives, globalization, product innovation, dynamic markets, and new methods of taking on and managing financial risk are key catalysts to profit growth and evolution. Wide-scale adoption of high-performance computing like that powered by AMD Opteron processors has further accelerated this financial services transformation. Proactive Enterprise Risk Management ("ERM") has become critical in managing the many activities and various risks that a modern financial firm is exposed to. When determining the soundness of an institution, financial regulators are increasingly assessing both the quantity of the firm's ERM initiatives and the quality of its ERM programs and infrastructure. Compliance risk management is an integral component of ERM.

Tags: Security Standards, Cost Control - Risk Mgmt.