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Title Date Added Company

High Performance Computing: Compatible Acceleration Using Fine Grain, Parallel Processing 2006-10-24 CPU Technology

In many cases, organizations are not realizing expected performance increases when running large, complex applications on High Performance Computing (HPC) computers. A mismatch between existing computer architectures and the applications running on them is exacerbating the inefficiencies inherent in these systems. Tailoring a computer to meet the specific resource requirements of a group of applications can yield an optimal machine without the massive expense in time and dollars of changing the architecture and rewriting the software. Multi-processor in Memory (MNM) technology, combined with CPU Tech's System-on-a-Chip (SoC) integration, can produce high throughput compatible processing at very low power and cost.

Tags: Parallel Processing, High Performance Computing

Quad-Core and Dual-Core Intel Xeon Processor-Based Two-Processor Workstations: Superior Performance to Improve How People Work and Create Every Day 2006-10-01 Intel

With more complex designs and an overwhelming desire to push the envelope of business, creative, and scientific possibilities, the challenges get tougher every year. Yet, these are what drives one at Intel to take the next leap in technologies so they can reach their objectives. With Intel technologies built into one's work environment, one can build success into the business. Intel continues to build more capabilities into platforms so the user can do much more with a lot less. For over 30 years, Intel has helped developers and businesses solve their toughest problems with advanced computing capabilities and technologies - from the first multi-purpose processor in 1974 to the industry's first quad-core, 64-bit processor-based platforms today.

Tags: Workstations

Hardware Support for Spin Management in Overcommitted Virtual Machines 2006-09-20 Association for Computing Machinery

Multiprocessor Operating Systems (OSs) pose several unique and conflicting challenges to System Virtual Machines (System VMs). For example, most existing system VMs resort to gang scheduling a guest OS's virtual processors (VCPUs) to avoid OS synchronization overhead. However, gang scheduling is infeasible for some application domains, and is inflexible in other domains. In an overcommitted environment, an individual guest OS has more VCPUs than available physical processors (PCPUs), precluding the use of gang scheduling. In such an environment, the authors demonstrate a more than two-fold in-crease in runtime when transparently virtualizing a chip-multiprocessor's cores.

Tags: Virtualization

Evaluation of ESX Server Under CPU Intensive Workloads 2006-09-06 Brigham Young University

Virtual machines are used by IT departments to provide better hardware utilization and to isolate users and programs from each other. The paper explores how configuration changes affect the throughput of virtual machines hosted on ESX Server during CPU intensive workloads. In particular the paper explores how Hyper-Threading, Virtual SMP, and the amount of RAM allocated affect throughput. Hyper-Threading is Intel's implementation of simultaneous multithreading technology and was introduced with the Xeon processor. Virtual SMP allows ESX Server to host virtual machines with two virtual processors.

Tags: Virtualization

Extending the World's Most Popular Processor Architecture: New Innovations That Improve the Performance and Energy Efficiency of Intel Architecture 2006-12-22 01:00:22 Intel

Intel has a long history of innovation in adding new capabilities to computer architecture and enabling the industry to deliver advanced applications with greater performance and capability. From the original Intel 8086 to the recent addition of Supplemental Streaming SIMD Extensions 3 (Supplemental SSE3) found in Intel Core 2 Duo processors, Intel has led the charge in expanding the capabilities of the world's most popular and broadly used computer architecture - Intel architecture. Continuing the history of innovation, this latest expansion of Intel architecture constitutes the most impactful instructions since SSE2 and represents the next major leap in Intel's fast-paced trajectory to deliver products with superior performance, capability, and energy-efficiency for years to come.

Intel Architecture and Silicon Cadence: The Catalyst for Industry Innovation 2006-12-27 01:00:55 Intel

Intel has a long history of setting the pace of industry innovation with the relentless pursuit of Moore's Law. This pace of innovation has served the ever increasing needs of users by providing the ability to increase processor performance, and deliver new features and capabilities, through innovation in processor architecture. As one looks at the continuation of this evolution, the industry needs an increased and more predictable pace of innovation to deliver platforms that can provide faster, more connected, trusted, personalized and natural computing experiences. Intel has embarked on a coordinated and accelerated pace of architecture innovation based on its industry-leading silicon expertise, and its architecture design capabilities that will provide the growth driver for the next decade and beyond.

Intel Energy-Efficient Performance: Performance Made Energy Efficient Through New Technological Leaps 2006-12-27 01:00:55 Intel

The drive for more performance is relentless, but is now matched with a need for greater energy efficiency-performance made energy efficient. Intel is addressing this need by delivering unprecedented innovations in processor architecture, silicon, platform technologies, and software. These innovations are delivering superior performance in the most efficient ways to give people what they care about most - whether it's smaller devices, increased performance, lower cooling bills, or better energy-efficiency.

Adaptive Sensing and Image Processing With a General-Purpose Pixel-Parallel Sensor/Processor Array Integrated Circuit 2006-09-01 Institute of Electrical and Electronics Engineers

In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMP-3 vision chip, comprising 128 × 128 array, fabricated in a 0.35µm CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed.

Tags: Parallel Processing

Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization 2006-08-10 Intel

The first generation of Intel Virtualization Technology (VT) for IA-32 and Itanium processors provides hardware support that simplifies processor virtualization, enabling reductions in Virtual Machine Monitor (VMM) software size and complexity. Resulting VMMs can support a wider range of legacy and future Operating Systems (OSs) on the same physical platform while maintaining high performance. In this paper, the authors provide details of the virtualization challenges posed by IA-32 and Itanium processors; present an overview and furnish details of VT-x (Intel Virtualization Technology for the IA-32 architecture) and VT-i (Intel Virtualization Technology for the Itanium architecture); show how VT-x and VT-i address virtualization challenges; and finally provide examples of usage of the VT-x and VT-i architecture.

Tags: Virtualization

Floating Point Calculations and the ANSI C, C++, and Fortran Standard 2006-08-01 Intel

High application performance is an important goal of the Intel compilers, even at default optimization levels. A number of optimizations involve transformations including: evaluation of constant expressions at compile time, hoisting invariant expressions out of loops, and changes in the order of evaluation of expressions that are not consistent with a strict interpretation of the ANSI or ISO standards for C, C++, and Fortran. These can result in differences in rounding and small variations in floating point results, which may be more or less accurate than the ANSI-conformant result. The Intel compilers provide command-line options that request the compiler not to perform optimizations that may be inconsistent with strict ANSI standards.

Tags: Programming Languages, Application Development

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Title	Date Added	Company
High Performance Computing: Compatible Acceleration Using Fine Grain, Parallel Processing	2006-10-24	CPU Technology
In many cases, organizations are not realizing expected performance increases when running large, complex applications on High Performance Computing (HPC) computers. A mismatch between existing computer architectures and the applications running on them is exacerbating the inefficiencies inherent in these systems. Tailoring a computer to meet the specific resource requirements of a group of applications can yield an optimal machine without the massive expense in time and dollars of changing the architecture and rewriting the software. Multi-processor in Memory (MNM) technology, combined with CPU Tech's System-on-a-Chip (SoC) integration, can produce high throughput compatible processing at very low power and cost. Tags: Parallel Processing, High Performance Computing
Quad-Core and Dual-Core Intel Xeon Processor-Based Two-Processor Workstations: Superior Performance to Improve How People Work and Create Every Day	2006-10-01	Intel
With more complex designs and an overwhelming desire to push the envelope of business, creative, and scientific possibilities, the challenges get tougher every year. Yet, these are what drives one at Intel to take the next leap in technologies so they can reach their objectives. With Intel technologies built into one's work environment, one can build success into the business. Intel continues to build more capabilities into platforms so the user can do much more with a lot less. For over 30 years, Intel has helped developers and businesses solve their toughest problems with advanced computing capabilities and technologies - from the first multi-purpose processor in 1974 to the industry's first quad-core, 64-bit processor-based platforms today. Tags: Workstations
Hardware Support for Spin Management in Overcommitted Virtual Machines	2006-09-20	Association for Computing Machinery
Multiprocessor Operating Systems (OSs) pose several unique and conflicting challenges to System Virtual Machines (System VMs). For example, most existing system VMs resort to gang scheduling a guest OS's virtual processors (VCPUs) to avoid OS synchronization overhead. However, gang scheduling is infeasible for some application domains, and is inflexible in other domains. In an overcommitted environment, an individual guest OS has more VCPUs than available physical processors (PCPUs), precluding the use of gang scheduling. In such an environment, the authors demonstrate a more than two-fold in-crease in runtime when transparently virtualizing a chip-multiprocessor's cores. Tags: Virtualization
Evaluation of ESX Server Under CPU Intensive Workloads	2006-09-06	Brigham Young University
Virtual machines are used by IT departments to provide better hardware utilization and to isolate users and programs from each other. The paper explores how configuration changes affect the throughput of virtual machines hosted on ESX Server during CPU intensive workloads. In particular the paper explores how Hyper-Threading, Virtual SMP, and the amount of RAM allocated affect throughput. Hyper-Threading is Intel's implementation of simultaneous multithreading technology and was introduced with the Xeon processor. Virtual SMP allows ESX Server to host virtual machines with two virtual processors. Tags: Virtualization
Extending the World's Most Popular Processor Architecture: New Innovations That Improve the Performance and Energy Efficiency of Intel Architecture	2006-12-22 01:00:22	Intel
Intel has a long history of innovation in adding new capabilities to computer architecture and enabling the industry to deliver advanced applications with greater performance and capability. From the original Intel 8086 to the recent addition of Supplemental Streaming SIMD Extensions 3 (Supplemental SSE3) found in Intel Core 2 Duo processors, Intel has led the charge in expanding the capabilities of the world's most popular and broadly used computer architecture - Intel architecture. Continuing the history of innovation, this latest expansion of Intel architecture constitutes the most impactful instructions since SSE2 and represents the next major leap in Intel's fast-paced trajectory to deliver products with superior performance, capability, and energy-efficiency for years to come.
Intel Architecture and Silicon Cadence: The Catalyst for Industry Innovation	2006-12-27 01:00:55	Intel
Intel has a long history of setting the pace of industry innovation with the relentless pursuit of Moore's Law. This pace of innovation has served the ever increasing needs of users by providing the ability to increase processor performance, and deliver new features and capabilities, through innovation in processor architecture. As one looks at the continuation of this evolution, the industry needs an increased and more predictable pace of innovation to deliver platforms that can provide faster, more connected, trusted, personalized and natural computing experiences. Intel has embarked on a coordinated and accelerated pace of architecture innovation based on its industry-leading silicon expertise, and its architecture design capabilities that will provide the growth driver for the next decade and beyond.
Intel Energy-Efficient Performance: Performance Made Energy Efficient Through New Technological Leaps	2006-12-27 01:00:55	Intel
The drive for more performance is relentless, but is now matched with a need for greater energy efficiency-performance made energy efficient. Intel is addressing this need by delivering unprecedented innovations in processor architecture, silicon, platform technologies, and software. These innovations are delivering superior performance in the most efficient ways to give people what they care about most - whether it's smaller devices, increased performance, lower cooling bills, or better energy-efficiency.
Adaptive Sensing and Image Processing With a General-Purpose Pixel-Parallel Sensor/Processor Array Integrated Circuit	2006-09-01	Institute of Electrical and Electronics Engineers
In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMP-3 vision chip, comprising 128 × 128 array, fabricated in a 0.35µm CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed. Tags: Parallel Processing
Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization	2006-08-10	Intel
The first generation of Intel Virtualization Technology (VT) for IA-32 and Itanium processors provides hardware support that simplifies processor virtualization, enabling reductions in Virtual Machine Monitor (VMM) software size and complexity. Resulting VMMs can support a wider range of legacy and future Operating Systems (OSs) on the same physical platform while maintaining high performance. In this paper, the authors provide details of the virtualization challenges posed by IA-32 and Itanium processors; present an overview and furnish details of VT-x (Intel Virtualization Technology for the IA-32 architecture) and VT-i (Intel Virtualization Technology for the Itanium architecture); show how VT-x and VT-i address virtualization challenges; and finally provide examples of usage of the VT-x and VT-i architecture. Tags: Virtualization
Floating Point Calculations and the ANSI C, C++, and Fortran Standard	2006-08-01	Intel
High application performance is an important goal of the Intel compilers, even at default optimization levels. A number of optimizations involve transformations including: evaluation of constant expressions at compile time, hoisting invariant expressions out of loops, and changes in the order of evaluation of expressions that are not consistent with a strict interpretation of the ANSI or ISO standards for C, C++, and Fortran. These can result in differences in rounding and small variations in floating point results, which may be more or less accurate than the ANSI-conformant result. The Intel compilers provide command-line options that request the compiler not to perform optimizations that may be inconsistent with strict ANSI standards. Tags: Programming Languages, Application Development