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 TitleDate AddedCompany
whitepaper Do Newer Processors Equate to Slower Applications?2007-05-16 JupiterMedia
  Processor speeds have hit the wall with current technologies. The speed is nearly at the maximum that can be obtained, and people are virtually at the ceiling with current technology. Some additional speed will be tweaked and added, but overall it seems that using current processor technology, the maximum speed of a processor is just about upon users.

Tags: Software Engineering, Application Development		   
whitepaper Achieving Application Scalability on Multi-Core Systems: Concurrency Solutions From Rogue Wave Software and Intel2007-05-14 Intel
  Building successful concurrent applications is a critical skill IT teams must have in order to meet the rising performance and scalability needs of the next generation of applications. Application developers must find ways to more efficiently process the increasing volume of data moving through the data center so that the business can reduce capital expenditures, increase scalability, and take advantage of new business opportunities. Intel's Core Duo and quad-core processors provide increasing processing power to those developers prepared to take advantage of them. The combination of Rogue Wave Hydra and Intel multi-core technologies and tools can help developers reach new levels of performance and scalability for business applications.

Tags: .NET, Application Development		   
whitepaper Tuning C++ Applications for the Latest Generation X64 Processors With PGI Compilers and Tools2007-05-09 Advanced Micro Devices (AMD)
  At CUG 2006, a cache oblivious implementation of a two dimensional Lagrangian hydrodynamics model of a single ideal gas material was presented. This paper presents further optimizations to this C++ application to allow packed, consecutive-element storage of vectors, some restructuring of loops containing neighborhood operations, and adding type qualifiers to some C++ pointer declarations to improve performance. In addition to restructuring of the application, analysis of the compiler-generated code resulted in improvements to the latest PGI C++ compiler in the area of loop-carried redundancy elimination, resolution of pointer aliasing conflicts, and vectorization of loops containing min and max reductions. These restructuring and compiler optimization efforts by PGI and Sandia have resulted in application speedups of 1.25 to 1.80 on the latest generation of x64 processors.

Tags: Programming Languages, Application Development		   
whitepaper Techniques for Efficient Processing in Runahead Execution Engines0000-00-00 University of Texas
  Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occurs. Previous research has shown that this technique significantly improves processor performance. However, the efficiency of runahead execution, which directly affects the dynamic energy consumed by a runahead processor, has not been explored. A runahead processor executes significantly more instructions than a traditional out-of-order processor, sometimes without providing any performance benefit, which makes it inefficient. This paper describes the causes of inefficiency in runahead execution and proposes techniques to make a runahead processor more efficient, thereby reducing its energy consumption and possibly increasing its performance.

Tags: Parallel Processing		   
whitepaper Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns0000-00-00 University of Texas
  While runahead execution is effective at parallelizing independent long-latency cache misses, it is unable to parallelize dependent long-latency cache misses. To overcome this limitation, this paper proposes a novel technique, Address-Value Delta (AVD) prediction. An AVD predictor keeps track of the address (pointer) load instructions for which the arithmetic difference (i.e., delta) between the effective address and the data value is stable. If such a load instruction incurs a long-latency cache miss during runahead execution, its data value is predicted by subtracting the stable delta from its effective address. This paper describes how, why, and for what kind of loads AVD prediction works and evaluate the design tradeoffs in an implementable AVD predictor.

Tags: Parallel Processing		   
whitepaper Workloads for Niagara: Customer Deployments of Sun Niagara CMT Systems One Year On2007-05-01 Sun Microsystems
  This paper explores customer adoption of the Niagara processor since its market introduction in December 2005, focusing on the range of workloads that are running today on this Chip MultiThreaded (CMT) platform. In addition, IDC has interviewed customers who have adopted Niagara to learn about the IT requirements that Niagara addresses - and the deployment patterns found in those sites. Sun Microsystems has innovated in the area of multicore processor technology, introducing its Niagara processors in December 2005. Each processor contains eight cores, and each of those cores supports four threads, or streams, of jobs. This means hat any single Niagara processor can support up to 32 independent threads of processing, making it an efficient engine to host parallelized, multithreaded workloads.   
whitepaper Processor Power Management in Windows Vista and Windows Server Longhorn2007-04-22 Microsoft
  Windows Vista and Windows Server Code Name "Longhorn" include updated support for ACPI Processor Power Management (PPM) features, including support for processor performance states and processor idle sleep states on multiprocessor systems. This paper provides details of the support in Windows Vista, describes how PPM works with Windows Vista power policy, provides guidelines to BIOS developers and system designers, and includes details on how Windows Vista may be tuned to optimize the balance between performance and power savings.

Tags: Windows Vista		   
whitepaper ELSC: Scalable Linux Scheduling on a Symmetric Multi-Processor Machine0000-00-00 University of Michigan
  Concerns about the scalability of multithreaded network servers running on Linux have prompted to investigate possible improvements to the Linux scheduler. The purpose of the research discussed in this paper is to improve the scalability of the Linux scheduler in order to prepare it for industrial-strength computational chores. The problem focuses on determining why time spent in the Linux scheduler increases with the number of threads executing in the system. It is determined that this problem's cause is a direct result of the scheduler's task selection process. This paper proposes a scheduler design alternative based on the static and dynamic portions of "Goodness", implement that design, and compare the implementation with the current Linux scheduler.

Tags: Linux - Open Source, Linux Server OS		   
whitepaper Feedback Directed Implicit Parallelism2007-04-10 Association for Computing Machinery
  This paper presents an automated way of using spare CPU resources within a shared memory multi-processor or multi-core machine. The approach is to profile the execution of a program; from this to identify pieces of work which are promising sources of parallelism; recompile the program with this work being performed speculatively via a work-stealing system and then to detect at run-time any attempt to perform operations that would reveal the presence of speculation.

Tags: Parallel Processing		   
whitepaper Quad-Core Processors Bring Higher Performance and Lower Cost to Mainstream Computing2007-04-01 Intel
  This paper explores the market adoption of and customer value proposition and adoption plans for the Quad-Core Intel Xeon processor 5300 series since its market introduction in 2006, focusing on workloads that are designed to run on multicore and multisocket platforms. In addition to discussing the range of workloads, IDC has interviewed customers who are adopting the Quad-Core Intel Xeon processor 5300 series to learn about the IT requirements that they are addressing and the deployment patterns found in those sites.

Tags: Data Center, ROI - TCO, Strategic Planning, High Performance Computing