| Title | Date Added | Company | |
|---|---|---|---|
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Introducing Quad-Core for the Data Center | 2007-04-01 | Intel |
This narrated slide presentation outlines the benefits of Quad-Core Intel Xeon processors 5300 series, which are purpose-built to help you:
Tags: Data Center, ROI - TCO, High Performance Computing, Virtualization |
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Quad-Core Processors Bring Higher Performance and Lower Cost to Mainstream Computing | 2007-04-01 | IDG (International Data Group) |
| This paper explores the market adoption of and customer value proposition and adoption plans for the Quad-Core Intel Xeon processor 5300 series since its market introduction in 2006, focusing on workloads that are designed to run on multicore and multisocket platforms. In addition to discussing the range of workloads, IDC has interviewed customers who are adopting the Quad-Core Intel Xeon processor 5300 series to learn about the IT requirements that they are addressing and the deployment patterns found in those sites. | |||
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Sun Fire X2100 M2 Server and Sun Fire X2200 M2 Server System Architecture | 2007-04-01 | Sun Microsystems |
| Sun Fire x64 servers featuring AMD Opteron processors are more than just a family of servers. These systems provide the modular infrastructure organizations need to rapidly deploy new solutions and adjust to changing business demands. The Sun Fire X2100 and Sun Fire X2200 servers set a new standard for low cost, high performance, entry-level computing. With an architecture that continues to set world records for performance, the Sun Fire X2100 and Sun Fire X2200 servers offer sophisticated functionality in an easy to cool compact design. Combined with a choice of operating systems and scalable system management tools, the Sun Fire X2100 and Sun Fire X2200 servers give organizations powerful, manageable servers that can help simplify the data center.
Tags: Application Servers, High Performance Computing |
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Optimizing Oracle's Siebel Applications for the Sun Platform, Solaris 10 OS, and UltraSPARC T1 Processor | 2007-04-01 | Sun Microsystems |
| This paper discusses the performance optimization of a complete Siebel Enterprise solution on the Sun platform using UltraSPARC T1 and UltraSPARC IV+ processor based servers. Also presented in detail is information on tuning the Solaris Operating System (OS) tuning, Siebel 7.7 tuning, Oracle Database 10g server tuning, Sun storage tuning and Sun Java System Web Server tuning. Additionally, unique features of the Solaris 10 OS that reduce risk while helping improve the performance and stability of Siebel applications are discussed. All of the techniques discussed here are lessons learned from a series of performance tuning studies, which were conducted under the auspices of the Siebel Platform Sizing and Performance Program (PSPP).
Tags: Processors, Sun Solaris |
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Power and Cooling in the Datacenter | 2007-03-29 | Advanced Micro Devices (AMD) |
| Today's datacenter is more than a room built to house rack upon rack of servers - it is a complex system. In fact, datacenters have become so complex - with so many interactions among processors, rack systems, power and cooling systems, storage arrays, networks, and communications channels - that they can be regarded as ecosystems, requiring only the input of energy to become a world in themselves, while supporting virtually all critical business and scientific computing needs both inside and outside an enterprise. The escalating speed, capacity, and power density of datacenter components have increased the degree of interdependence typically required for maximum performance and cost-effectiveness. Processor power, chip density, and the resulting power consumption and heat can have a profound effect on datacenter operational costs.
Tags: Data Center |
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A SystemC Transaction Level Model for the MIPS R3000 Processor | 2007-03-29 | Concordia University |
| Processor cores in embedded applications build today the cornerstone of System-on-Chip designs. Among the most successful RISC (Reduced Instruction Set Computer) cores are the MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. This paper designs and verifies a Transaction Level Modeling (TLM) architecture of the MIPS R3000 in SystemC. The TLM in SystemC is adopted so that abstract data types can be used for higher level modeling and faster simulation. The processor is implemented such that the instruction and data caches contain all the necessary instructions and data to eliminate complex memory access management, respectively.
Tags: RISC-Based Servers |
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Multi-Core and Linux Kernel | 2007-03-27 | Intel |
| Semiconductor technological advances in the recent years have led to the inclusion of multiple CPU execution cores in a single processor package. This processor architecture is known as Multi-Core (MC) or Chip Multi Processing (CMP). Any application which is well optimized and scales with SMP will take immediate benefit of the multiple execution cores, provided by the Multi-core architecture. Even if the application is single-threaded, multi-tasking environment will take advantage of these multiple execution cores. 2.6 Linux kernels take instant advantage of the MC architecture. MC also brings in performance optimization opportunities which will further enhance the performance. This paper captures the recent enhancements to the 2.6 Linux Kernel which better support and enhance the performance of Multi-core capable platforms.
Tags: Linux Server OS |
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Motivating Commodity Multi-Core Processor Design for System-Level Error Protection | 2007-03-23 | Hewlett-Packard (HP) |
| This paper analyzes the reliability and availability features in several commodity Chip MultiProcessors (CMPs) and finds that they have numerous single points of failure. Failures in some system components, e.g., interconnect cache controller and memory controller logic, leave CMPs susceptible to error even if the computation is Dual Modular Redundant (DMR) or Triple Modular Redundant (TMR). Furthermore, even though some replicated resources are present in CMPs, they can not be used effectively for providing system-level protection because of the lack of fault isolation in shared components. This paper describes a CMP design that can provide system-level error protection. The proposed design provides mode configuration features in hardware to tolerate errors in any component. | |||
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Can a File System Virtualize Processors? | 2007-03-20 | Association for Computing Machinery |
| Supercomputers comprise more and more processors and these processors are increasingly heterogeneous, with differing performance characteristics. The conventional programming models assume that all nodes run in lockstep. Thus, applications run at the speed of the least powerful processor. This paper introduces DesyncFS, a new programming model based on the block abstraction of traditional file systems. It virtualizes the performance characteristics of processors; this allows their heterogeneity to be hidden. The paper shows that DesyncFS allows cluster throughput to scale with average processor throughput instead of being limited by the slowest processor.
Tags: Supercomputers |
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IBM System i5 520 With POWER5 Performance in a JD Edwards EnterpriseOne Mixed Workload Environment | 2007-03-15 | IBM |
| IBM recently announced a new family of high-speed IBM System i servers with POWER5 technology. Customers with older hardware are asking if they can expect comparable performance on these new systems with similar CPW ratings. The answer is yes. The IBM Oracle International Competency Center (IOICC) and the IBM Rochester development team conducted a series of mixed-workload performance tests on both an older four-way IBM System i 820 and a new IBM System i5 520 uni-processor system. The tests ran both JD Edwards EnterpriseOne ERP 8.0 Web users and multiple streams of batch workloads singly and concurrently.
Tags: Application Servers, ERP |
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