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 TitleDate AddedCompany
whitepaper Design of a Data Recovery Block for Communications Over Power Distribution Networks of Microprocessors2008-06-18 Institute of Electrical and Electronics Engineers
  This paper proposed the use of Power Distribution Network (PDN) of a microprocessor for ubiquitous access of internal nodes for test/debug and showed the suitability of impulse Ultra-WideBand (UWB) communications for the purpose. This paper presents design of a data recovery block to recover data from UWB impulses superposed on a power line of a microprocessor. Considerations for data recovery block design based upon measured PDN characteristics have been discussed. The proposed circuit was implemented in TSMC 0.18 um CMOS process, and simulations show that it consumes 4.42 mW when operating from a 1.8V supply and at a pulse repetition rate of 200 MHz.

Tags: Data Recovery - Security		   
whitepaper An Assessment of Leadership Performance With POWER6 Processors and Red Hat Enterprise Linux 5.12008-01-31 IBM
  Compute-intensive performance is increasingly required for today's high-performance environments. The IBM System p 570 with POWER6 processors provides leadership performance and demonstrates excellent scalability moving from one node to four nodes in this environment while providing linear SMP (Symmetric Multiprocessing) scaling and growth for workloads similar to the metrics used here. This paper highlights the exceptional performance on IBM's POWER6 processor-based systems running with the latest Red Hat Enterprise Linux (RHEL) 5.1 operating system, based on recently audited published SPEC CPU2006 and SPECjbb2005 results, including single-system LINPACK metrics on System p 570 4-core, 8-core and 16-core systems. With Simultaneous Multithreading (SMT) support turned on, Linux is easily able to provide effective scheduling support of the 32 processor threads seen on the 16-core 570 system.

Tags: Processors, Linux Server OS		   
whitepaper Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm2008-01-08 Northwestern University
  Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and in particular work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the required compression hardware. This paper presents a lossless compression algorithm that has been designed for on-line memory hierarchy compression, and cache compression in particular. They reduced the algorithm to a register transfer level hardware implementation, permitting performance, power consumption, and area estimation.

Tags: Software Engineering, High Performance Computing		   
whitepaper This Might Be the Last Place You'd Expect to Find an Intel Processor2008-01-01 Intel
  Finding a processing platform that runs so efficiently has been challenging for developers like GD Canada. Proprietary technology can offer the performance and power efficiency needed, but such solutions are often vendor-specific, take a very long time to develop and deploy, and can be quite costly to maintain, let alone upgrade. Intel really attacked the thermal output and power consumption problem when they came out with the Intel Pentium M processor and associated chipsets. Shortly after Intel launched the Intel Pentium M processor, the U.S. Army announced the Future Combat System (FCS) program, a move to standardize the Army's entire vehicle computing infrastructure on a common product.

Tags: Processors		   
whitepaper Energy-Aware Microprocessor Synchronization: Transactional Memory Vs. Locks2008-01-01 Brown University
  One important way in which multiprocessors differ from uniprocessors is in the need to provide programmers the ability to synchronize concurrent access to memory. Transactional memory was proposed as a way of improving throughput especially when the rate of synchronization conflict is low. This paper explores power implications of transactional memory on standard and synthetic benchmarks. They propose a new "Serial execution" mode that lowers energy consumption during high contention periods by reducing transaction throughput. They conclude that transactional models are a promising approach to low-power synchronization, and serial execution strengthens the energy advantage, but that further work is needed to fully understand how transactions compare to locks at high levels of contention.

Tags: Processors		   
whitepaper Intel Centrino With VPro Technology and Intel Core2 Processor With VPro Technology2007-12-01 Intel
  Intel Centrino with vPro technology-based notebooks and Intel Core2 processor with vPro technology-based desktop PCs1 deliver built-in security and remote management capabilities to meet critical business challenges. IT administrators can now quickly identify and contain more security threats, take more accurate asset and hardware/software inventories remotely, resolve more software and OS problems faster without leaving the service center, and accurately diagnose hardware problems down-the-wire. IT organizations can now spend less time on routine tasks, and can focus resources where they are most needed for better security and manageability of both notebook and desktop PCs.   
whitepaper Accelerating EDA Application Performance with 45nm Quad-Core Processors2007-11-20 Intel
  Intel IT and Synopsys conducted a joint performance assessment of 64-bit Intel multi-core platforms running Synopsys Proteus* application for optical proximity correction (OPC).

Tags: Embedded Microprocessors, Data Mining - Analysis, Database Management, Data Recovery - Security		   
whitepaper Introducing the 45nm Next-Generation Intel Core Microarchitecture2007-11-01 Intel
  In the second half of 2007, Intel started producing of the next-generation Intel Core2 processor family codenamed "Penryn." The Penryn processor family is based on industry-leading 45-nanometer (nm) High-k metal gate silicon technology and latest microarchitecture enhancements. This next evolution in Intel Core microarchitecture builds on the tremendous success of revolutionary microarchitecture and marks the next step in Intel's rapid cadence for delivering a new process technology with enhanced microarchitecture or an entirely new microarchitecture every year.   
whitepaper IBM POWER6 Microprocessor Physical Design and Design Methodology2007-11-01 IBM
  The IBM POWER6e microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, Random Logic Macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

Tags: Methodology		   
whitepaper System Power Management Support in the IBM POWER6 Microprocessor2007-11-01 IBM
  The IBM POWER6 microprocessor chip supports advanced, dynamic power management solutions for managing not just the chip but the entire server. The design facilitates a programmable power management solution for greater flexibility and integration into system- and data-center-wide management solutions. The design of the POWER6 microprocessor provides real-time access to detailed and accurate information on power, temperature, and performance. Together, the sensing, actuation, and management support available in the POWER6 processor, known as the EnergyScalee architecture, enables higher performance, greater energy efficiency, and new power management capabilities such as power and thermal capping and power savings with explicit performance control. This paper provides an overview of the innovative design of the POWER6 processor that enables these advanced, dynamic system power management solutions.