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 TitleDate AddedCompany
whitepaper Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams2004-04-10 Massachusetts Institute of Technology
  This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Raw supports both ILP and streams by routing operands between architecturally-exposed functional units over a point-to-point scalar operand network. This network offers low latency for scalar data transport.

Tags: Application Development		   
whitepaper Porting Linux to the M32R Processor2003-05-21 Renesas Technology
  This paper has ported a Linux system to the Renesas M32R processor, which is a 32-bit RISC microprocessor designed for embedded systems, and with an on-chip-multiprocessor feature. So far, both of UP (Uni-Processor) and SMP (Sym-metrical Multi-Processor) kernels (based on 2.4.19) have been ported and they are operating on the M32R processor. A Debian GNU/Linux based system has been also developed on a diskless NFS-root environment, and more than 300 unofficial .deb packages have already been prepared for the M32R target. This paper describes this new architecture port in detail and explains the current status of the Linux/M32R project.

Tags: Processors, Linux - Open Source		   
whitepaper Design of a DSP Unit for 32-Bit Embedded EISC Microprocessor2002-10-17 Yonsei University
  This paper designed a low hardware cost and fast DSP unit for 32-bit embedded EISC (Expanded Instruction Set Computer) microprocessor. The DSP unit operates as a functional unit of an integer core. This architecture can reduce the hardware cost and control easily the pipeline of the processor. The MAC/MAS unit was designed using hybrid radix-4/radix-8 Booth algorithm to reduce the hardware cost. All of the DSP instructions except DSP XY memory MAC/MAS instructions are executed in single cycle and have single cycle throughput. This DSP unit was modeled in Verilog HDL and synthesized with 0.35 ?m standard cell libraries after verifications. Occupied area is 21,850 equivalent gates. It operates at 63 MHz clock speed under the worst-case conditions.

Tags: Embedded Microprocessors		   
whitepaper Adapting Processor Supply Voltage to Instruction-Level Parallelism2001-12-01 University of Pittsburgh
  Low power consumption is one of the most important design constraints for modern computer systems. One promising technique to lowering power consumption of microprocessors is to reduce supply voltage and clock speed. By running at lower voltages and clock speeds, a quadratic savings in power can be achieved. This paper describes a technique for adjusting supply voltage and frequency at run-time to save energy. The technique monitors a program's Instruction-Level Parallelism (ILP) and adjusts processor voltage and speed in response to the amount of observed ILP. The technique lets the user specify goal performance, which the hardware maintains while running at the lowest energy settings.

Tags: Processors, Parallel Processing		   
whitepaper RSA BSAFE Encryption Software Helps a Leading Chip Maker Optimize the Performance of Its Processors2005-06-15 03:00:01
  AMD is a leading supplier of integrated circuits for the computing, communications and consumer electronics markets. AMD engaged RSA Security to optimize its RSA BSAFE Crypto-C and RSA BSAFE Crypto-C Micro Edition developer toolkits so that application developers could take advantage of the enhanced power of the AMD64 processors. Offering one of the widest ranges of data encryption and signing algorithms available today, RSA BSAFE technology is designed to make it easy for developers to incorporate premier encryption technologies into diverse applications including digitally signed forms, private Internet communications, tamper-resistant applications and secure wireless communications.   
whitepaper Intel, Nexcom and huperLab Introduce a Mega Surveillance System2005-06-15 03:00:01
  Random threats to public safety - such as terrorist attacks - are fueling demand for better security surveillance in public venues. To confront today's security risks, the digital security surveillance (DSS) industry needs scalable hardware platforms that meet a high performance threshold. The ideal solution includes a high-density port count to power several cameras, high I/O bandwidth for streaming real-time video, and strong processing for D1 video quality and compression. Nexcom applied its expertise in blade system platform design to come up with a high-density/high-performance solution for DSS applications.   
whitepaper Digital-Logic Finds Intel Pentium M Processor an Ideal Fit for Developing Embedded PCs2005-06-15 03:00:01
  Originally designed for mobile systems such as notebook computers, the Intel Pentium M processor features high performance, low power consumption and a flat, fanless design to meet the specific requirements of this computing arena. But these same characteristics also suit this processor to embedded applications, a market segment where developers are putting it to good use. This case study describes how Switzerland-based Digital-Logic AG - a leading provider of embedded computing solutions - came to rely on a Pentium M processor platform to develop a highly integrated PC module that serves as both the core component of in-house product design and the basis of third-party solutions built by system OEMs.   
whitepaper EmergeCore Networks Goes From Concept to Product in Seven Months With Help From the Intel Media Switch IXE2412 10/100 Device and Embedded Intel Architecture2005-06-15 03:00:01
  As broadband access becomes more of a commodity, Internet service providers and local exchange carriers are shifting their focus from merely providing a high-speed Internet connection to the enhanced revenue potential of value-added services. The problem for carriers and service providers is how to deliver new multiple high-bandwidth services to a large population of end-users, without saturating the network. To solve this problem, EmergeCore Networks has created a mesh network that integrates the EC Reactor Open IP Services Platform. This innovative design is based on the combination of the Intel Media Switch IXE2412 10/100 Device and an embedded Intel architecture design that features the Intel Pentium III processor and other building blocks.   
whitepaper Corrent Security Appliances Sustain Maximum Throughput - Even Under Attack2005-06-15 03:00:01
  Corrent needed server motherboards that offered different levels of I/O capability and performance. Plus, Corrent engineers wanted motherboards with the IPMI interface to allow for remote management, thereby making it possible to deploy multiple appliances across an enterprise while managing them from a single console. Corrent met all of their performance and price needs with Intel architecture. Today, Corrent engineers use Intel processors, chipsets and server boards in a variety of configurations to scale solutions according to the performance and price requirements of different customers.   
whitepaper Intel Case Study: ADLINK Technology2005-06-15 03:00:01
  In this case study, three embedded Intel Architecture components form the foundation for two entirely different processing platforms: one for a mobile application, the other for a telecom storage application. This case study explains how the Intel Pentium M processor, Intel 855GME chipset, and Intel 6300ESB I/O controller hub help ADLINK deliver high-performance, low-power modular platforms for extremely fast time-to-market in two very different solutions.