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 TitleDate AddedCompany
whitepaper Warp Processors2006-07-01 Association for Computing Machinery
  This paper describes a new processing architecture, known as a warp processor that utilizes a Field-Programmable Gate Array (FPGA) to improve the speed and energy consumption of software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, re-implements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region.

Tags: Processors		   
whitepaper Solving Power and Cooling Challenges for High Performance Computing2006-06-01 Intel
  It takes a comprehensive strategy to scale High Performance Computing (HPC) capabilities, while simultaneously containing power and cooling costs. New Dual-Core Intel Xeon and Intel Itanium processor-based servers offer a critical new resource, delivering dramatic increases in performance, price/performance and energy-efficiency across a broad range of HPC applications. This paper explains this and other Intel advances that can help to increase density, reduce costs and scale capacity in the existing facilities.

Tags: Application Servers, High Performance Computing		   
whitepaper Preparing for Peta-Scale2006-06-01 Intel
  It was few years before a TFLOPS system was found in a commercial company; but it is predicted that it will be less than two years from the first PFLOPS systems to the first petaflops solution being deployed in industry. But converting peta-scale potential into achieved business value is not automatic. To benefit from peta-scale computing, one needs to understand where peta-scale capacity and capabilities are coming from, and take the right steps to prepare for it. This paper explains how.

Tags: Parallel Processing, High Performance Computing		   
whitepaper Preparing Applications for Intel Core Microarchitecture2006-06-01 Intel
  Intel Core microarchitecture combines the best of the desktop Intel NetBurst microarchitecture and mobile Intel Pentium M architecture. As Intel will be using a single architecture for both the desktop and mobile platforms, the challenge is how to prepare applications so that they can run well on Intel Core microarchitecture. What can be done with existing and new desktop and mobile applications to make them ready when the new Intel processors hit the market? This paper is not intended to show users everything they can do to improve the performance of existing applications on the Intel Core microarchitecture. It only suggests some techniques to either improve or maintain the performance of an existing application when running on systems with these new Intel processors.

Tags: Processors, High Performance Computing		   
whitepaper Windows Vista Feature Focus: 64-Bit (x64) Support2006-05-25 Penton Media
  The x64 versions of Windows Vista adopt all of the positive and negative quirks of their XP x64 predecessor and add a few wrinkles of their own. Like XP x64, the various Vista x64 versions support x64-compatible PCs based on the AMD-64 (Athlon-64, Opteron, Turion processors) and Intel EMT-64 (Pentium D and Xeon) platforms. Unlike XP x64, users don't need to buy a x64-specific versions of Vista. Instead, all Windows Vista editions, except for Vista Starter, will come with both 32-bit (x86) and 64-bit (x64) versions in the box, on separate DVDs.

Tags: Windows XP, Windows Vista		   
whitepaper Multiple Instruction Stream Processor2006-05-09 Institute of Electrical and Electronics Engineers
  Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting thread-level parallelism in the software. To support this trend, the paper presents a novel processor architecture called the Multiple Instruction Stream Processing (MISP) architecture. MISP introduces the sequencer as a new category of architectural resource, and defines a canonical set of instructions to support user-level inter-sequencer signaling and asynchronous control transfer. MISP allows an application program to directly manage user-level threads without OS intervention. By supporting the classic cache-coherent shared-memory programming model, MISP does not require a radical shift in the multithreaded programming paradigm.

Tags: Processors		   
whitepaper Intel Core Microarchitecture: Setting New Standards for Energy-Efficient Performance2006-04-24 Microsoft
  This paper discusses Intel Core microarchitecture, the foundation for the new Intel architecture-based desktop, mobile, and mainstream server multi-core processors that will begin appearing in the marketplace in the second half of 2006. This scalable, multi-core optimized, power-efficient microarchitecture delivers a number of innovative features that will set new standards for energy-efficient performance, enabling a new wave of innovation across desktop, server, and mobile platforms. The information provided in this paper applies to Microsoft Windows Server "Longhorn", Microsoft Windows Vista, Microsoft Windows Server 2003, Microsoft Windows XP, and Microsoft Windows 2000.

Tags: Windows XP, Windows Vista		   
whitepaper A Low-Power Dual-VDD Microprocessor for General Purpose Correlation Applications2006-04-23 University of Michigan
  This paper presents a 143 MHz 16-bit RISC microprocessor. The processor includes a reconfigurable multiplier that was customized for correlation algorithms. Low-power techniques such as dual-Vdd (2.5/1.8V) and clock gating reduced power by 39% without compromising performance. In addition to the correlator, an I/O interface is included that allows for multichannel interconnect to the external environment.

Tags: TDMA - CDMA		   
whitepaper Optimizing Operand Transport Using Dynamic SIMDization in Multimedia Systems2006-04-11 Georgia Institute of Technology
  For multimedia processing, modern Instruction-Level Parallel (ILP) processors are faced with limited parallelism and inevitable communication issues, as silicon feature size decreases and pipelines become wider. This paper proposes and evaluates a dynamic optimization mechanism that exploits regular operand distribution patterns in multimedia applications. The proposed methodology; improves performance by recognizing and extracting more parallelism than conventional ILP processors; lowers the burden of operand transport by localizing the communication between instructions based on the operand characteristics; and maintains binary compatibility by applying run-time optimization rather than requiring changes to the ISA, recompilation with a vectorizing compiler, or manual retargeting and optimization.

Tags: Parallel Processing, Multimedia		   
whitepaper Dual Processor Vs Dual Core2006-03-25 Puget Custom Computers
  As the tasks that computers can perform get more complicated, and as people desire to do more at once, computer manufacturers are trying hard to increase speed in order to keep up with demand. Having a faster CPU has been the traditional way to keep up, since a faster CPU can do a task then quickly switch and work on the next. However, due to size, complexity and heat issues it has become increasingly difficult to make CPUs faster. In order to continue to improve performance, another solution had to be found.

Tags: Motherboards