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 TitleDate AddedCompany
whitepaper Speculative Threading: Creating New Methods of Thread-Level Parallelization2005-12-01 Intel
  This paper discusses the factors that are driving the need for speculative threading. It will then explain a new speculative threading model developed within Intel's research labs. Preliminary performance results using this model indicate the potential for significant processing gains with only a small increase in power requirements. Tomorrow's computing workloads from RMS and other applications of the future will require exponential increases in computing power. Multi-core platforms and multithreading are paving the way to meeting these performance needs. To do it though, they require a companion effort in accelerating the development of the thread-level parallelism necessary for reaching their full performance potential.   
whitepaper Speculative Threading: Creating New Method of Thread-Level Parallelization2005-12-01 Intel
  A new era of computing has begun and the word "Multi" provides a key clue. This new era will be characterized by multi-core processors enabling single-die multiprocessing of multithreaded applications. Signaling the start of this new era is the emergence of new workloads and usage models into mainstream computing. Intel is conducting extensive research on some of these new workloads, particularly those associated with Recognition, Mining and Synthesis (RMS). Multi-core processors are essential in helping attain this computing power. Intel researchers have been investigating a number of compiler techniques and microarchitectures that can provide highly threaded code through the use of speculative threading. This paper discusses the factors that are driving the need for speculative threading.

Tags: Parallel Processing		   
whitepaper A Power-Aware Run-Time System for High-Performance Computing2005-11-18 Association for Computing Machinery
  The High-Performance Computing (HPC) community has focused on performance, where performance is defined as speed. To achieve better performance per compute node, microprocessor vendors have not only doubled the number of transistors (and speed) every 18-24 months, but they have also doubled the power densities. Consequently, keeping a large-scale HPC system functioning properly requires continual cooling in a large machine room, thus resulting in substantial operational costs. Furthermore, the increase in power densities has led to a decrease in system reliability, thus leading to lost productivity. To address these problems, this paper proposes a power-aware algorithm that automatically and transparently adapts its voltage and frequency settings to achieve significant power reduction and energy savings with minimal impact on performance.

Tags: Processors, High Performance Computing		   
whitepaper Heterogeneous Chip Multiprocessors2005-11-01 Institute of Electrical and Electronics Engineers
  Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a much wider spectrum of system loads - from low to high thread parallelism - with high efficiency.

Tags: ASICs - Chip Sets		   
whitepaper The MIPS32 24KE Core Family: High-Performance RISC Cores With DSP Enhancements2005-10-24 MIPS Technologies
  The MIPS32 24KE core family is the latest high-performance synthesizable microprocessor cores from MIPS Technologies, Inc. and features DSP enhancements at a negligible cost. The 24KE core family fills an important gap in the convergence of RISC processors and Digital Signal Processors (DSPs). This convergence is enabled by emerging market trends, and comes with cost advantages and technical challenges. The 24KE design meets these challenges quite handily as shown in this paper. The 24KE cores were built by adding the new DSP enhancements to the existing pipeline in the 24K cores. The performance benefit for DSP applications from these enhancements can be as much as two times compared to a 24K design.

Tags: RISC-Based Servers, High Performance Computing		   
whitepaper Intel Embedded Compact Extended Form Factor Single Board Computer Interface2005-10-01 Intel
  The Single Board Computer (SBC) small form factor solution has become increasingly important for meeting the challenges of the embedded environment. This paper serves both as an open standard form factor specification reference, and a white paper discussion of a proof-of-concept board. The Intel Embedded Compact Extended Form Factor (Intel ECX Form Factor) is an embedded, non-standard body, open standard, small form factor (SFF) single board computer. It is one of the industry's smallest and most widely adopted SBC form factors. The dimensions of the Intel ECX Form Factor SBC are 105 mm x 146 mm.

Tags: Interfaces - Buses - I-Os, Embedded Microprocessors		   
whitepaper Improving Application Efficiency Through Chip Multi-Threading2005-10-01 Sun Microsystems
  Chip multi-threading (CMT) brings to hardware the concept of multi-threading, similar to software multi-threading. A CMT-enabled processor, similar to software multi-threading, executes many software threads simultaneously within a processor on cores. So in a system with CMT processors, software threads can be executed simultaneously within one processor or across many processors. Executing software threads simultaneously within a single processor increases a processor's efficiency as wait latencies are minimized. The paper introduces CMT technology, such as chip multi-processing (CMP), chip multi-processing with hardware threads, and simultaneous multi-threading, from a software developer's perspective.

Tags: Software Engineering		   
whitepaper The Evolution of Build-Up Package Technology and Its Design Challenges2006-04-04 02:54:05
  This paper reviews Sequential Build-Up (SBU) laminate substrate development from its beginning in 1988. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for Application-Specific Integrated Circuit (ASIC) and microprocessor packaging applications.   
whitepaper Improving the Performance of Embedded Superscalar Microprocessors by Adding Partial Pipelines2005-08-20 University of York
  This paper introduces adding a "Partial" pipeline to a base embedded superscalar microprocessor implementation to achieve cost effective performance improvements. This method is exemplified by adding a "Partial" Integer Pipeline (IP) to the TriCore TM 2.0 MCU/DSP core. The "Partial" IP pipeline, designed based on TriCore 2.0 simulation results of the EEMBC benchmark suite, executes a subset of TriCore 2.0 IP instructions. They used the basic block sampling and simulation technique to simulate enhanced TriCore 2.0 models, and obtained results indicating that adding the partial IP pipeline can achieve similar performance improvements to duplicating the full IP pipeline. Their approach can be applied to the early design stages of microprocessor development in order to explore design spaces.

Tags: Embedded Microprocessors		   
whitepaper Building Cutting-Edge Server Applications: Intel Xeon Processor Family Features the Intel NetBurst Microarchitecture With Hyper-Threading Technology2005-08-04 Intel
  The Intel NetBurst microarchitecture significantly enhances P6 microarchitecture as well as introduces new innovative performance related features, such as Execution Trace Cache, Rapid Execution Engine, Hyper-Pipelined technology, and Streaming SIMD Extensions 2. It also triples the throughput on the system bus, allowing the Intel Xeon processor family to deliver industry-leading performance and over the next several years. But typically (even with highly optimized code), not all of the available execution resources are used during each clock cycle, due to dependencies, memory latencies and data bottlenecks. Hyper-Threading technology provides two logical processors on each physical processor and lets applications execute separate tasks on each logical processor. This increases the utilization of resources on the processor, thereby reducing bottlenecks and increasing throughput for multi-threaded applications.

Tags: Application Servers, High Performance Computing