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Title Date Added Company

Measuring the Value of Intel Core2 Processor With VPro Technology in the Enterprise 2006-08-01 Intel

This paper presents the results of research, sponsored by Intel and conducted by Wipro Product Strategy & Architecture (PSA) practice, designed to examine the potential impact of Intel Core 2 processor with vPro technology on the total cost of ownership (TCO) for business desktop PCs. This analysis examines how the Intel Core 2 processor with vPro technology can help reduce infrastructure complexity, and how the technology affects manageability and IT costs. In addition, this research extends concepts originally described in Wipro's New Insights on PC Management study4, which detailed the relationship between infrastructure complexity and overall PC support costs.

Accelerating Security Applications With Intel Multi-Core Processors 2006-12-26 01:00:57 Intel

The transition to multi-core processors offers flexibility for development and optimization of higher performance applications. Multi-core architectures can significantly improve program flow so that cache memory associated with each execution core is used more effectively. With multiple caches, optimizing data locality is possible, driving higher cache-hit rates and improved overall application performance. Intel demonstrated over 6x performance improvement of an intrusion detection and prevention security application running on four processor cores (dual-core, dual-processor) - without threading the application. Such supra-linear performance improvements offer new opportunities for developers to inexpensively improve their applications while also achieving faster time-to-market.

Solving Power and Cooling Challenges for High Performance Computing 2006-12-26 01:00:57 Intel

It takes a comprehensive strategy to scale High Performance Computing (HPC) capabilities, while simultaneously containing power and cooling costs. New Dual-Core Intel Xeon and Intel Itanium processor-based servers offer a critical new resource, delivering dramatic increases in performance, price/performance and energy-efficiency across a broad range of HPC applications. This paper explains this and other Intel advances that can help to increase density, reduce costs and scale capacity in the existing facilities.

Preparing Applications for Intel Core Microarchitecture 2006-06-01 Intel

Intel Core microarchitecture combines the best of the desktop Intel NetBurst microarchitecture and mobile Intel Pentium M architecture. As Intel will be using a single architecture for both the desktop and mobile platforms, the challenge is how to prepare applications so that they can run well on Intel Core microarchitecture. What can be done with existing and new desktop and mobile applications to make them ready when the new Intel processors hit the market? This paper is not intended to show users everything they can do to improve the performance of existing applications on the Intel Core microarchitecture. It only suggests some techniques to either improve or maintain the performance of an existing application when running on systems with these new Intel processors.

Tags: High Performance Computing

A Low-Power Dual-VDD Microprocessor for General Purpose Correlation Applications 2006-11-10 01:00:17 University of Michigan

This paper presents a 143 MHz 16-bit RISC microprocessor. The processor includes a reconfigurable multiplier that was customized for correlation algorithms. Low-power techniques such as dual-Vdd (2.5/1.8V) and clock gating reduced power by 39% without compromising performance. In addition to the correlator, an I/O interface is included that allows for multichannel interconnect to the external environment.

Dual Processor Vs Dual Core 2006-04-27 07:26:13 Puget Custom Computers

As the tasks that computers can perform get more complicated, and as people desire to do more at once, computer manufacturers are trying hard to increase speed in order to keep up with demand. Having a faster CPU has been the traditional way to keep up, since a faster CPU can do a task then quickly switch and work on the next. However, due to size, complexity and heat issues it has become increasingly difficult to make CPUs faster. In order to continue to improve performance, another solution had to be found.

Local Temperature Control in Data Center Cooling: Part I, Correlation Matrix 2006-05-02 06:19:03 Hewlett-Packard

A data center is a computer room containing a dense aggregation of commodity computing, networking and storage hardware mounted in industry standard racks. With the evolution of microprocessor fabrication technology and the increasing demand of internet, power density has been growing from the chip level to the data center level. As a result, mechanical designers face the challenge of handling heat dissipation efficiently in a data center. This paper demonstrates the possibility of optimizing local temperature distribution using vent tiles. In the proposed experiments, the relationship between rack inlet temperature and vent tile configuration is analyzed, and used to demonstrate the effectiveness of a local control algorithm through a control simulation.

Local Temperature Control in Data Center Cooling: Part II, Statistical Analysis 2006-05-02 06:22:14 Hewlett-Packard

The data center plays a more and more important role with the increasing demands of internet and commodity computing. As a result of the evolution of the microprocessor and increasing demands of customers, the power density in data centers becomes much greater. Mechanical engineers face challenges in cooling system design. Recent research focuses on local control algorithms which can help to optimize local temperature distribution, and thus increase the energy efficiency of the system. This paper analyzes the relationship between rack inlet temperature and vent group configuration from the view of statistics. It also examines whether rack power can affect inlet temperature.

Energy Per Instruction Trends in Intel Microprocessors 2006-12-22 01:00:22 Intel

Energy Per Instruction (EPI) is a measure of the amount of energy expended by a microprocessor for each instruction that the microprocessor executes. This paper presents an overview of EPI, explain the factors that affect a microprocessor's EPI, and derive a historical comparison of the trends in EPI over multiple generations of Intel microprocessors. It shows that the recent Intel Pentium M and Intel Core Duo microprocessors achieve significantly lower EPI than what would be expected from a continuation of historical trends.

Achieving High-Resolution Video Using Scalable Capture, Processing, and Display 2007-01-07 01:00:31 Hewlett-Packard

New video applications are becoming possible with the advent of several enabling technologies: multicamera capture, increased PC bus bandwidth, multicore processors, and advanced graphics cards. This paper presents a commercially-available multicamera system and a software architecture that, coupled with industry trends, create a situation in which video capture, processing, and display are all increasingly scalable in the number of video streams. Leveraging this end-to-end scalability, the authors introduce a novel method of generating high-resolution, panoramic video. While traditional point-based mosaicking requires significant image overlap, authors gain significant advantage by calibrating using shared observations of lines to constrain the placement of images.

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Title	Date Added	Company
Measuring the Value of Intel Core2 Processor With VPro Technology in the Enterprise	2006-08-01	Intel
This paper presents the results of research, sponsored by Intel and conducted by Wipro Product Strategy & Architecture (PSA) practice, designed to examine the potential impact of Intel Core 2 processor with vPro technology on the total cost of ownership (TCO) for business desktop PCs. This analysis examines how the Intel Core 2 processor with vPro technology can help reduce infrastructure complexity, and how the technology affects manageability and IT costs. In addition, this research extends concepts originally described in Wipro's New Insights on PC Management study4, which detailed the relationship between infrastructure complexity and overall PC support costs.
Accelerating Security Applications With Intel Multi-Core Processors	2006-12-26 01:00:57	Intel
The transition to multi-core processors offers flexibility for development and optimization of higher performance applications. Multi-core architectures can significantly improve program flow so that cache memory associated with each execution core is used more effectively. With multiple caches, optimizing data locality is possible, driving higher cache-hit rates and improved overall application performance. Intel demonstrated over 6x performance improvement of an intrusion detection and prevention security application running on four processor cores (dual-core, dual-processor) - without threading the application. Such supra-linear performance improvements offer new opportunities for developers to inexpensively improve their applications while also achieving faster time-to-market.
Solving Power and Cooling Challenges for High Performance Computing	2006-12-26 01:00:57	Intel
It takes a comprehensive strategy to scale High Performance Computing (HPC) capabilities, while simultaneously containing power and cooling costs. New Dual-Core Intel Xeon and Intel Itanium processor-based servers offer a critical new resource, delivering dramatic increases in performance, price/performance and energy-efficiency across a broad range of HPC applications. This paper explains this and other Intel advances that can help to increase density, reduce costs and scale capacity in the existing facilities.
Preparing Applications for Intel Core Microarchitecture	2006-06-01	Intel
Intel Core microarchitecture combines the best of the desktop Intel NetBurst microarchitecture and mobile Intel Pentium M architecture. As Intel will be using a single architecture for both the desktop and mobile platforms, the challenge is how to prepare applications so that they can run well on Intel Core microarchitecture. What can be done with existing and new desktop and mobile applications to make them ready when the new Intel processors hit the market? This paper is not intended to show users everything they can do to improve the performance of existing applications on the Intel Core microarchitecture. It only suggests some techniques to either improve or maintain the performance of an existing application when running on systems with these new Intel processors. Tags: High Performance Computing
A Low-Power Dual-VDD Microprocessor for General Purpose Correlation Applications	2006-11-10 01:00:17	University of Michigan
This paper presents a 143 MHz 16-bit RISC microprocessor. The processor includes a reconfigurable multiplier that was customized for correlation algorithms. Low-power techniques such as dual-Vdd (2.5/1.8V) and clock gating reduced power by 39% without compromising performance. In addition to the correlator, an I/O interface is included that allows for multichannel interconnect to the external environment.
Dual Processor Vs Dual Core	2006-04-27 07:26:13	Puget Custom Computers
As the tasks that computers can perform get more complicated, and as people desire to do more at once, computer manufacturers are trying hard to increase speed in order to keep up with demand. Having a faster CPU has been the traditional way to keep up, since a faster CPU can do a task then quickly switch and work on the next. However, due to size, complexity and heat issues it has become increasingly difficult to make CPUs faster. In order to continue to improve performance, another solution had to be found.
Local Temperature Control in Data Center Cooling: Part I, Correlation Matrix	2006-05-02 06:19:03	Hewlett-Packard
A data center is a computer room containing a dense aggregation of commodity computing, networking and storage hardware mounted in industry standard racks. With the evolution of microprocessor fabrication technology and the increasing demand of internet, power density has been growing from the chip level to the data center level. As a result, mechanical designers face the challenge of handling heat dissipation efficiently in a data center. This paper demonstrates the possibility of optimizing local temperature distribution using vent tiles. In the proposed experiments, the relationship between rack inlet temperature and vent tile configuration is analyzed, and used to demonstrate the effectiveness of a local control algorithm through a control simulation.
Local Temperature Control in Data Center Cooling: Part II, Statistical Analysis	2006-05-02 06:22:14	Hewlett-Packard
The data center plays a more and more important role with the increasing demands of internet and commodity computing. As a result of the evolution of the microprocessor and increasing demands of customers, the power density in data centers becomes much greater. Mechanical engineers face challenges in cooling system design. Recent research focuses on local control algorithms which can help to optimize local temperature distribution, and thus increase the energy efficiency of the system. This paper analyzes the relationship between rack inlet temperature and vent group configuration from the view of statistics. It also examines whether rack power can affect inlet temperature.
Energy Per Instruction Trends in Intel Microprocessors	2006-12-22 01:00:22	Intel
Energy Per Instruction (EPI) is a measure of the amount of energy expended by a microprocessor for each instruction that the microprocessor executes. This paper presents an overview of EPI, explain the factors that affect a microprocessor's EPI, and derive a historical comparison of the trends in EPI over multiple generations of Intel microprocessors. It shows that the recent Intel Pentium M and Intel Core Duo microprocessors achieve significantly lower EPI than what would be expected from a continuation of historical trends.
Achieving High-Resolution Video Using Scalable Capture, Processing, and Display	2007-01-07 01:00:31	Hewlett-Packard
New video applications are becoming possible with the advent of several enabling technologies: multicamera capture, increased PC bus bandwidth, multicore processors, and advanced graphics cards. This paper presents a commercially-available multicamera system and a software architecture that, coupled with industry trends, create a situation in which video capture, processing, and display are all increasingly scalable in the number of video streams. Leveraging this end-to-end scalability, the authors introduce a novel method of generating high-resolution, panoramic video. While traditional point-based mosaicking requires significant image overlap, authors gain significant advantage by calibrating using shared observations of lines to constrain the placement of images.