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 TitleDate AddedCompany
whitepaper Accelerating EDA Application Performance with 45nm Quad-Core Processors2007-11-20 Intel
  Intel IT and Synopsys conducted a joint performance assessment of 64-bit Intel multi-core platforms running Synopsys Proteus* application for optical proximity correction (OPC).

Tags: Components, Data Tools, Data Infrastructure, Data Tools		   
whitepaper Statistical Static Timing Analysis Technology2007-10-01 Fujitsu
  With CMOS technology scaling down to the nanometer realm, process variations have been increased. In particular, the increase of delay variations has seriously affected the design periods and timing yields. To estimate more accurately these delay variations, Statistical Static Timing Analysis (SSTA), which considers delay variations statistically, has been proposed. SSTA is expected to shorten the design Turnaround Time (TAT) and predict the timing yields. Research on practical applications of SSTA has already been conducted at Fujitsu Laboratories. The paper has developed SSTA tools for use in designs for processors and Application Specific Integrated Circuits (ASICs) in cooperation with Fujitsu and Fujitsu VLSI. This paper describes the delay variations and basic SSTA techniques and introduces SSTA applications to Fujitsu's processor and ASIC design flows.

Tags: Data Tools		   
whitepaper Comparing Multi-Core Processors for Server Virtualization2007-11-13 Intel
  Rob Carpenter shares highlights from his whitepaper on his data center virtualization performance testing of the new Quad-Core Intel Xeon processor 7300 series.

Tags: Components, Components		   
whitepaper Optimization of Silicon Technology for the IBM System z92007-02-13 IBM
  IBM 90-nm Silicon-On-Insulator (SOI) technology was used for the key chips in the System z9 processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9 to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.

Tags: Server Hardware, Components		   
whitepaper Improving the Performance of Embedded Superscalar Microprocessors by Adding Partial Pipelines2005-08-20 University of York
  This paper introduces adding a "Partial" pipeline to a base embedded superscalar microprocessor implementation to achieve cost effective performance improvements. This method is exemplified by adding a "Partial" Integer Pipeline (IP) to the TriCore TM 2.0 MCU/DSP core. The "Partial" IP pipeline, designed based on TriCore 2.0 simulation results of the EEMBC benchmark suite, executes a subset of TriCore 2.0 IP instructions. They used the basic block sampling and simulation technique to simulate enhanced TriCore 2.0 models, and obtained results indicating that adding the partial IP pipeline can achieve similar performance improvements to duplicating the full IP pipeline. Their approach can be applied to the early design stages of microprocessor development in order to explore design spaces.

Tags: Components		   
whitepaper Taking It to the Next Level: The AMD Geode LX 800@0.9W Processor - Embedded X86 Processor Performance Rating System White Paper2005-05-20 Advanced Micro Devices (AMD)
  Clock speed is not the only factor that goes into performance, and with this study it is shown that it is logical to rate a processor based on a suite of recognized benchmarks. Memory subsystem, graphics, bus speed, and instructions per clock cycle all play a role in overall performance. The AMD Geode LX 800@0.9w processor earns its nomenclature based on the measured performance.

Tags: Components, Server Hardware		   
whitepaper Industry Focus: Airline0000-00-00 Accenture
  During both turbulent and smooth times, successful airline companies continuously invest in safety, security, and customer service enhancements. Accenture Technology Labs devises first class solutions that encompass every facet of the airline industry. They are exploring miniscule technology with massive safety potential for aircraft. "Smart Dust" will pack a sensor, power supply, analog circuitry, radio communication capability, and a programmable microprocessor into a package the size of a pinpoint. These sensors could be embedded into objects like a turbine blade on an aircraft and be able to transmit information to other sensors.

Tags: Components, Mobile and Wireless, 		  
whitepaper NAND Flash Applications Design Guide0000-00-00 Toshiba
  This detailed white paper from Toshiba America Electronic Components, Inc. provides product designers, engineers, and developers with information on how NAND Flash memory technologies can be effectively incorporated into the design and performance of consumer electronics products. The document presents the reader with an in-depth history of NAND Flash memory, and how this technology differs from NOR Flash, which is also used in various electronic devices. In addition, the guide discusses NAND Flash and hardware interfaces, the use of large block versus small block NAND Flash, failure mode identification and solutions, and the management of NAND Flash. Finally, the authors present a myriad of tips for using NAND Flash, and offer a brief overview of CompactFlash cards, a card product using NAND Flash rapidly being deployed in industry

Tags: Components		   
whitepaper Design of a DSP Unit for 32-Bit Embedded EISC Microprocessor2002-10-17 Yonsei University
  This paper designed a low hardware cost and fast DSP unit for 32-bit embedded EISC (Expanded Instruction Set Computer) microprocessor. The DSP unit operates as a functional unit of an integer core. This architecture can reduce the hardware cost and control easily the pipeline of the processor. The MAC/MAS unit was designed using hybrid radix-4/radix-8 Booth algorithm to reduce the hardware cost. All of the DSP instructions except DSP XY memory MAC/MAS instructions are executed in single cycle and have single cycle throughput. This DSP unit was modeled in Verilog HDL and synthesized with 0.35 ?m standard cell libraries after verifications. Occupied area is 21,850 equivalent gates. It operates at 63 MHz clock speed under the worst-case conditions.

Tags: Components		   

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