| Title | Date Added | Company | |
|---|---|---|---|
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Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance | 0000-00-00 | University of Texas |
| Runahead execution improves memory latency tolerance without significantly increasing processor complexity. Unfortunately, a runahead execution processor executes significantly more instructions than a conventional processor, sometimes without providing any performance benefit, which makes it inefficient. This paper identifies the causes of inefficiency in runahead execution and proposes simple -yet effective-techniques to make a runahead processor more efficient, thereby reducing its energy consumption. The proposed efficiency techniques reduce the extra instructions executed in a runahead processor from 26.5% to 6.2% without significantly affecting the 22%performance improvement provided by runahead execution.
Tags: Components, Server Hardware |
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Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance | 0000-00-00 | University of Texas |
| High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes bring data into the caches that are not needed by correct execution. This paper proposes the use of the first-level caches as filters that predict the usefulness of speculative memory references. With the proposed technique, speculative memory references bring data only into the first-level caches rather than all levels in the cache hierarchy. The processor monitors the use of the cache blocks in the first-level caches and decides which blocks to keep in the cache hierarchy based on the usefulness of cache blocks.
Tags: Components |
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DMA Support in KMDF Drivers | 2007-04-10 | Microsoft |
| The paper describes how Microsoft Windows drivers support Direct Memory Access (DMA) devices, using the Windows Driver Foundation (WDF) kernel-mode driver framework. Because understanding Windows DMA architecture is the key to properly implementing DMA drivers on Windows, this paper also describes the Windows DMA architecture and the Windows DMA abstraction.
Tags: Software Development Tools |
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RAMP-White: An FPGA-Based Coherent Shared Memory Parallel Computer Emulator | 2007-02-17 | IBM |
| RAMP-White is an FPGA-based coherent shared memory research platform. It is one of the three initial prototypes being developed by the RAMP (Research Accelerator for Multiple Processors) group. In the spirit of the RAMP project, RAMP-White has been architected to emphasize flexibility over raw performance. This paper describes the architecture of RAMP-White. RAMP-White is designed to provide a configurable coherent shared memory research platform while also demonstrating how large systems can be assembled using RAMP modules. The platform is sufficiently flexible to handle different coherency protocols, memory hierarchies and even processor ISAs and implementations.
Tags: Components, Software Development Tools |
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AMD Athlon 64 FX-60 Dual-Core Processor | 2006-08-15 | XtremeLab |
| Providing exceptional PC performance on games, digital media and intense applications, the AMD Athlon 64 FX-60 dual-core processor will allow enthusiasts to experience the next generation of multi-core supported games and applications using AMD's most powerful PC processor ever released. The core of the FX-60 is based on the "Toledo" core which everyone also knows from the Athlon 64 X2 4400+ and X2 4800+. The core is made at a 90nm fabrication procedure. It includes a DDR400 DDR memory controller built into the processor. The newer features like SSE3and XD-bit are also included.
Tags: Components |
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Inside Intel Core Microarchitecture and Smart Memory Access: An In-Depth Look at Intel Innovations for Accelerating Execution of Memory-Related Instructions | 2006-07-01 | Intel |
| The Intel Core microarchitecture is a new foundation for Intel architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art, power-efficient multi-core microarchitecture delivers increased performance and performance per watt, thus increasing overall energy efficiency. Intel Core microarchitecture extends the energy-efficient philosophy first delivered in Intel's mobile microarchitecture (Intel Pentium M processor), and greatly enhances it with many leading edge microarchitectural advancements, as well as some improvements on the best of Intel NetBurst microarchitecture. This new microarchitecture also enables a wide range of frequencies and thermal envelopes to satisfy different needs. This paper provides a brief look at the five major "Ingredients" of the Intel Core microarchitecture.
Tags: Components, Components, Mobile and Wireless |
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Maximizing Performance of Embedded Applications With Intel Flash Memory | 0000-00-00 | Intel |
| Intel offers a wide variety of flash memory hardware solutions designed to meet the diverse needs of embedded system designs. Intel's most comprehensive new product offering for the embedded market segment is Intel StrataFlash Embedded Memory (P30). This webcast shows how the P30 is the price-performance solution that is well-suited for embedded applications in market segments such as consumer electronics, wired communications and industrial. The webcast reviews factory programming modes to help designers overcome programming time bottlenecks, security features that can be optimized for each design, synchronous read modes that improve read performance, and low power operation features that provide flexibility for application needs.
Tags: Components, Components, |
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Understanding Shared Pool Memory Structures: Tips on How to Optimize Usage and Avoid Errors | 2005-09-01 | Oracle |
| The Oracle shared pool provides critical services for sharing of complex objects among large numbers of users. Prior to 10g R1, DBAs often spent much time learning about the shared pool memory management to configure and tune shared pool usage; with the tight time constraints and ever-changing workloads, many found this task daunting. The Automatic Shared Memory Management (ASMM) features introduced in 10gR1 solved this problem by providing the DBA a simple, automatic self-tuning mechanism for configuring shared memory components of the SGA, including the buffer cache and shared pool. The Automatic Database Diagnostic Monitor (also introduced in 10gR1) further simplified shared pool related tuning efforts by providing automatic diagnosis and recommendations for application specific issues.
Tags: LAN - WAN, Components, |
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Paving the Road to a PC Refresh | 2005-08-25 | Insight Direct |
| If you've got aging computers with low memory and lagging speed, your end users' productivity is undoubtedly hampered. Of course, enterprise PC refreshes require significant investments beyond an initial outlay for hardware and software. You must also take into account the costs associated with installation, training, administration, technical support, and eventual disposal. Download this on-demand Webinar from Insight and Lenovo for a comprehensive discussion of the PC refresh cycle and what you need to consider as you plan for yours.
Tags: IT Infrastructure, Components, Components, Components, Client System Hardware, Client System Hardware, IT Budgeting, IT Budgeting, User Satisfaction, |
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Intel 910GML/915G/915GM/915GMS/915GV and 910GL Express Chipsets: Intel Dynamic Video Memory Technology (DVMT) 3.0 | 2005-08-01 | Intel |
| The purpose of this white paper is to describe the memory allocation and usage model scenarios of an Intel Graphics Media Accelerator Driver feature, Intel Dynamic Video Memory Technology (DVMT) for the Intel 910GML/915G/915GM/915GMS915GV and 910GL Express chipsets. This white paper will provide details on how DVMT works, configurability options available to the OEM and descriptions of what to expect in certain scenarios of DVMT 3.0.
Tags: Components, Components |
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