Binary LNS-Based Naive Bayes Inference Engine for Spam Control: Noise Analysis and FPGA Implementation

Overview

A hardware architecture for naive Bayes inference engine in the context of e-mail content classification for spam control is proposed. The inference engine utilizes the Logarithmic Number System (LNS) to simplify naive Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. This paper developed a noise model for the inference engine and analyzed the noise bounds, which determine the inference accuracy. The inference engine design is synthesized targeting the Altera Stratix FPGA device. The synthesized inference engine was functionally verified versus a MATLAB implementation.