A 10000 Fps CMOS Sensor With Massively Parallel Image Processing

Overview

A high speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 µm standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 µm x 35 µm pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values.