By Tom Krazit
Friday, June 02 2006 10:50 AM
URL: http://www.zdnetasia.com/news/hardware/0,39042972,39362560,00.htm

SUNNYVALE, Calif.--Advanced Micro Devices plans to stretch its capabilities over the next few years, believing that flexibility will be a key part of its designs over the rest of the decade.

AMD on Thursday laid out plans to serve 30 percent of the market within the next two years, with new quad-core processor designs scheduled for 2007 and an acceleration of its manufacturing capabilities.

The company also talked about plans to build future processors with the ability to mix and match the building blocks of a chip to cater to different needs, and to allow its partners to add co-processors that can link directly to Opteron processors through AMD's Hypertransport links.

Executives speaking to analysts and press at the company's headquarters here sought to maintain the momentum AMD has enjoyed over the last three years, gaining market share in important markets and giving Intel fits. "We want to open up our technology and unleash a completely new wave of innovation," said Hector Ruiz, CEO of AMD.

The chipmaker plans to license its Hypertransport technology to allow customers and third-party chipmakers to build specialized processors and other chips that can connect directly to future Opteron processors, said Marty Seyer, senior vice president at AMD. Hewlett-Packard, Sun Microsystems, IBM and Cray have all agreed to participate in the program, which AMD is calling Torrenza.

Ultimately, AMD wants to separate the building blocks for its chips--such as processing cores, memory controllers, Hypertransport links and cache memory--into distinct parts that can be configured in multiple ways to meet changing workload requirements, said Phil Hester, AMD's chief technology officer. This also will allow customers to plug co-processors built specifically for certain workloads, such as Java or XML (Extensible Markup Language) traffic, right into Opteron chips, he said.

AMD's partners have been able to sign up for noncoherent licenses to Hypertransport up until this point, Hester said in an interview after the briefings. The new licenses provide a coherent link to the chipset and will allow server users to manage different co-processors with drivers, like PC peripherals, rather than having to use new applications for each co-processor, he said.

The difference between noncoherent links and coherent links is the difference between a co-processor being treated as an adjunct to the system and it being treated like another Opteron processor, said Nathan Brookwood, an analyst at Insight 64. A coherent link allows a specialized high-performance co-processor to access data stored in the cache memory of the Opteron processors. This could prove useful for applications such as cryptography or media processing, he said.

On the manufacturing front, AMD plans to introduce chips based on its 45-nanometer manufacturing technology by the middle of 2008, said Daryl Ostrander, senior vice president for logic technology and manufacturing at the company. That would mean a 1.5-year gap between the introduction of AMD's first 65-nanometer chips later this year and the volume production of 45-nanometer chips, he said. The number attached to the size of the manufacturing technology refers to the average size of features on the chip. Smaller features allow chipmakers to pack more transistors and more performance into their chips.

Intel has been losing market share to AMD in several areas over the last few years, but it has maintained an advantage in introducing new manufacturing technologies ahead of everyone else in the industry. Intel is already shipping a 65-nanometer chip, its Core Duo processor. Some in the chip-manufacturing industry have called for chipmakers to slow their cadence of shrinking transistors to every three years as the challenges become more daunting, but Intel has stuck to a two-year schedule. However, AMD's plan is to move from 65 nanometers to 45 nanometers in 18 months, which will allow it to chip away at Intel's advantage, Ostrander said.

Later in the day, Ostrander said that the 18-month turnaround for 45 nanometers was set because of AMD's confidence in that generation of its technology, but wouldn't necessarily serve as the cadence for future rollouts. Next on the agenda is 32 nanometers, which AMD will hopefully introduce 18 to 24 months after the 45-nanometer chips arrive in production volumes, he said.

By 2008, AMD will be ready to introduce something called Direct Connect 2.0 for server processors, Hester said. Direct Connect is the name AMD uses for its chip designs, which use an integrated memory controller to link directly to memory and Hypertransport links to connect to other processors or a system's I/O (input/output) controller. Details about Direct Connect 2.0 were not immediately available.

The company plans to introduce quad-core processors for servers and desktops in mid-2007, as it outlined at the recent Spring Processor Forum, and mobile chips based on a new power-optimized architecture. Hester revealed a few extra details about the quad-core chips on Thursday, disclosing that each core in a mid-2007 server processor will have either four 16-bit Hypertransport links or eight 8-bit links for connecting to other cores or processors.

Power management...

This, along with the introduction of a third layer of cache memory shared between cores in the quad-core design, will allow AMD's customers to build SMP (symmetric multiprocessing) servers that can compete with Unix vendors, Hester said. AMD will also maintain a dual-core design for desktops during this time period.

Hester also talked about plans for a new mobile-processor design that implements better power management. AMD just released its first dual-core chip for notebooks. It plans to improve that chip by building power management technologies that can shut down a processing core or system links as demanded by the processing requirements, he said. The quad-core chips also will be able to take advantage of this power-management technology.

AMD is using the same basic core design for its new mobile architecture, but it's improving the power sensitivity of its memory controller, Hester said. The current memory controller used on AMD's Turion mobile chips was originally designed for servers and isn't completely appropriate for the notebook market. The new design will be able to turn on and off in response to workloads, the same way the processing cores react to ebbs and flows in processing requests, Hester said.

The decision to finally develop a chip architecture designed completely for a mobile environment fills a hole in AMD's lineup, said Richard Shim, an analyst at IDC. Notebooks are the fastest-growing part of the PC market, and while AMD has had some success against Intel in this segment, it hasn't duplicated its efforts in the server and desktop segments.

Seyer also announced vague plans for two new technologies code-named Trinity and Raiden. Trinity is software that's designed to bring security, virtualization and management capabilities to both servers and clients. Raiden is a new kind of commercial thin-client architecture that focuses on moving the processing into the server room. The company provided few details about these announcements.

Seyer, tracked down after the briefings, was able to share a little bit more about Raiden. AMD believes that the thin clients of the future won't necessarily be like the underpowered thin clients of the past. Virtualization technologies emerging in AMD's chips could allow for several different types of thin clients. Sometimes, they may run like traditional thin clients, where all the processing is done on a server. Other times the user might want to do more processing on their side.

AMD wants to develop a combination of hardware and software that can provide different levels of "thickness" in clients and servers, Seyer said. But he provided no time frame or specific product plan