By Tom Krazit
Wednesday, September 27 2006 09:47 AM
URL: http://www.zdnetasia.com/news/hardware/0,39042972,61955440,00.htm

SAN FRANCISCO--Intel has built a prototype of a processor with 80 cores that can perform a trillion floating-point operations per second.

CEO Paul Otellini held up a silicon wafer with the prototype chips before several thousand attendees at the Intel Developer Forum here Tuesday. The chips are capable of exchanging data at a terabyte a second, Otellini said during a keynote speech. The company hopes to have these chips ready for commercial production within a five-year window.

Intel uses its twice-yearly conference to educate developers on its long- and short-term plans. Over three days, hardware developers and partners get a chance to interact with Intel employees and take classes on new technologies.

As expected, Intel announced plans to have quad-core processors ready for its customers in November. An extremely fast Core 2 Extreme processor with four cores will be released then, and the newly named Core 2 Quad processor for mainstream desktops will follow in the first quarter of next year, Otellini said.

The quad-core server processors are on a similar trajectory, with a faster Xeon 5300 processor scheduled for November and a low-power Xeon slated for the first quarter. Intel's first quad-core processors are actually two of its dual-core Core architecture chips combined into a multichip package.

"Performance matters again," Otellini said, disclosing that the quad-core desktop processor will deliver 70 percent faster integer performance than the Core 2 Duo, and the quad-core server processor will be 50 percent faster than the Xeon 5100 introduced in June.

One reason performance didn't matter to Intel during the last couple of years was because it was getting trounced on benchmarks at the hands of Advanced Micro Devices' Opteron and Athlon 64 server and desktop processors. That all changed with the introduction of the Core 2 Duo chips this year.

"With this new set of dual and quad-core processors, we've regained our leadership," Otellini told developers. The growing Internet video phenomenon, as evidenced by the spectacular rise of Web sites like YouTube, will keep these processors busy during intensive tasks like video editing, he said.

Road to Santa Rosa
Notebooks will get a face-lift next year with the Santa Rosa platform, which will provide notebooks with new technologies like 802.11n wireless and flash memory. Intel believes that it will be the first to add flash memory to a notebook motherboard, which will improve boot times and reduce power consumption, Otellini said.

System power consumption is only one part of the equation. During the next few years, Intel wants to improve the performance per watt of power consumption of its transistors by 300 percent through new manufacturing technologies and designs, Otellini said. The next step on that road, Intel's 45-nanometer manufacturing technology, will enable the company to build chips that deliver a 20 percent improvement in performance with five times less current leakage, he said.

But the ultimate goal, as envisioned by Intel's terascale research prototype, is to enable a trillion floating-point operations per second--a teraflop--on a single chip. Ten years ago, the ASCI Red supercomputer at Sandia National Laboratories became the first supercomputer to deliver 1 teraflop using 4,510 computing nodes.

Intel's prototype uses 80 floating-point cores, each running at 3.16GHz, Justin Rattner, Intel's chief technology officer, said in a speech following Otellini's address. In order to move data in between individual cores and into memory, the company plans to use an on-chip interconnect fabric and stacked SRAM (static RAM) chips attached directly to the bottom of the chip, he said.

Intel's work on silicon photonics, including its recent announcement of a silicon laser, could help contribute toward the core-to-core connection challenge. Rattner and professor John Bowers of the University of California at Santa Barbara demonstrated Intel's newest breakthrough model of silicon laser, which was constructed using conventional techniques that are better suited to volume manufacturing than older iterations of the laser.

Many of the architectural nuances of the 80-core chip can be traced back to earlier research breakthroughs announced at previous IDFs. Connecting chips directly to each other through tiny wires is called Through Silicon Vias, which Intel discussed in 2005. TSV will give the chip an aggregate memory bandwidth of 1 terabyte per second.

Intel, meanwhile, began to discuss replacing wires with optical technology in computers and chips in 2001 and has come out with several experimental parts for enabling lasers and optical technology to replace wires.

The same year, Intel began to warn about the dangers of heat dissipation in processors. One of the solutions, the company said at the time, lay in producing chips with multiple cores.

CNET News.com's Michael Kanellos contributed to this report.