The chip industry is changing the recipe for its transistors to continue improving performance for another generation.

For almost 40 years, chipmakers have been building transistor gates--the basic switch in a transistor--out of silicon. But Intel, IBM and Advanced Micro Devices now plan to introduce new materials for transistor gates that significantly cut power leakage while dramatically improving performance, company executives said this week in separate announcements.

Silicon Valley will not have to be renamed, as silicon remains the basic material for the chip and that's not changing anytime soon. However, the gates themselves will now be made out of metal, and a thin layer that sits between the gate and the rest of the transistor--called a gate oxide--will also use a different building block.

"When you've been using silicon dioxide and polysilicon gates for 40 years and make that jump to a different set of materials, and surpass that performance, it's quite an achievement," said Mark Bohr, an Intel senior fellow and director of the company's advanced transistor research.

Intel plans to use the materials in its Penryn family of chips scheduled for introduction later this year and built with Intel's 45-nanometer manufacturing technology. It demonstrated systems running on those chips on Thursday for a group of reporters and analysts.

"This really speaks to the level of maturity that we've now gotten from the process," said Intel CEO Paul Otellini, during a briefing for reporters at Intel's headquarters in Santa Clara, Calif. "When they first described this to me, as a layman, I thought, 'this couldn't possibly work.' And you've seen what they've done," he said, gesturing at a row of servers and desktops running the 45-nanometer Penryn family of chips with the new transistor technology.

IBM and AMD also plan to use metal gates and high-k gate oxides when they are ready to start building chips using 45-nanometer technology in 2008, said Bernie Meyerson, chief technology officer of IBM's chip group. (A material designated as "high-k" means it can hold more electrical charge than other materials.) IBM and AMD have an agreement to collaborate on research into future chipmaking techniques. The two companies also worked on the advance with Toshiba and Sony, IBM's partners on the Cell processor inside the Playstation 3.

"For us, it's an extraordinary time. This is an enormous departure from the previous history," Meyerson said. IBM has chips running in its manufacturing plants using the new transistors, he said.

Transistors operate when electrical current either flows or doesn't flow through the channel of the transistor. So, they are either "on" or "off," the mechanical representation of the 0s and 1s that make up basic computer language. To shut the gate, a voltage is applied and current is prevented from moving through the channel.

Every two years or so, the chip industry finds ways to build smaller transistors, allowing chipmakers to cram more and more transistors onto a single chip. This improves performance and makes sure Intel keeps co-founder Gordon Moore an honest man for another generation of products.

Plugging leaks in transistors...

But as companies make smaller transistors, plugging leaks becomes a huge problem. As gate dielectrics get thinner and thinner--currently about five atoms wide--electrical current can leak out, creating a situation in which the transistor isn't really on and isn't really off. Leaky current also creates excess heat and causes all sorts of system problems.

The enormously expensive chipmaking process means that companies tend to stick with materials they know, said Dan Hutcheson, president of VLSI Research. Finding new materials that can control leakage, operate faster than the older materials and endure repeated manufacturing by the millions is quite a challenge.

"We haven't changed a material in the transistor since the '60s," Hutcheson said.

Switching to a combination of metal gates and high-k dielectrics appears to be the answer to controlling leakage and keeping Moore's Law alive. High-k dielectrics can be made thicker than silicon dioxide dielectrics, decreasing current leakage and giving chip designers another couple of generations in which they can continue to make transistors smaller.

"You've taken what was a layer too thin to scale, and made a layer whose electrical properties are what you need, but the difference is it's vastly thicker," IBM's Meyerson said. "You can then scale this into the future."

But high-k materials can't really be used with conventional silicon gates, Intel's Bohr said. The silicon gate wouldn't be able to switch between states as quickly as usual because of problems in the interaction between the silicon gate and the high-k dielectric. So, Intel identified metals that it can use for both positive and negative transistors to solve that problem and make sure the gates continue to switch very quickly. IBM and AMD will likewise use metal gates with the new dielectrics, Meyerson said.

The exact combination of the metals and the high-k gate dielectric is key, Bohr said. The dielectric is based on the element hafnium, but he declined to specify the exact recipe used to build the new transistors. "Identifying the right combination is a very significant accomplishment, and we're not going to give that away for free," he said.

IBM also declined to comment on the specific nature of its high-k material, but it has published research in the past about using hafnium for this purpose, Meyerson said.

Intel first used the combination of metal gates and high-k dielectrics on the test SRAM (static RAM) chips it built using its 45-nanometer technology, Bohr said. The dielectric must be built using atomic-layer deposition, he said, meaning that a machine must deposit the dielectric just one atomic layer--the width of a single atom--at a time.

The companies diverge, however, when it comes to the methods they will use to build these transistors. IBM and AMD plan to use a technique called immersion lithography, in which the lines on the chip are etched while it is immersed in purified water. Intel is sticking with its current techniques, but might consider using immersion lithography for its 32-nanometer chips, Bohr said. Likewise, Intel will continue using its 193-nanometer dry lithography tools, bucking a trend toward immersion lithography pursued by companies like IBM and AMD.